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Fri, 6 Nov 2026 17:16:32 +0100 From: Gabriel Fernandez Subject: [PATCH v4 0/8] clk: stm32mp25: add Cortex-M0 D3 clocks, ETR/STM and USB2PHY1 STP Date: Fri, 6 Nov 2026 17:16:30 +0100 Message-ID: <20261106-ups_mp25_clk_update-v4-0-9e32b817c38d@foss.st.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAF/97WoC/43N0QqCMBTG8VeJXTfZzrE5u+o9ImTOsxxlijMpx HdvBhFUF13+Pzi/M7FAvafAtquJ9TT64NtLjHS9YrY2lyNxX8VmIEBJAcCvXSiaDjaFPZ+Ka1e ZgXjmpBFYSqscsHjZ9eT87anuD7FrH4a2vz+fjHJZXx7+9EbJBadcKMoMalvizrUhJGFIbNuwR RzhDwWigrmuMNVktKu+FXwrUqjfCkYlNQhOaSlz+lDmeX4AStgp60QBAAA= To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Gabriel Fernandez , Krzysztof Kozlowski , Gwenael Treuveur X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dWnlJ3eCOPmtVQr55R2deW9luB7rRl0sIgLNJVPcFdEkA3PdlZKKNEqu+BfsU8u1V/83NOi+Qinv8Y/Cu37wT8ORmuAFq7Ga0J5YoG6Yh08hAGwxTaxmGsaETRQ4xfVplnLv+/DwnwaLS8CJN+K9Yk5AtWMwx9AzhB31XRmgtc2bHcCITv97mXdTw+0JU0vD8LEvU4Mmw5p5hTaAAwDKioCauOIGHQvwt5yHiMGIVAptin6u+VJBNnuMk411Z6lCmgSs1uKcfQMzgUf6ReM+afAWm9GOTAJGAH2gElZsGw8di97FQMG1DEKeK079QD/v8LOEJuAUPz2eXEb+oCnvhv4wLW8C+g8fRYPmSDES6uWrssXhYSvIj0LL2lR8n31o+hl9x+HYe6VNnubmbeikXH8p2cyksoJb+1frc0tZJkMavbVs6Vj0UKA/IsrwxTDS X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 16:16:32.6842 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 65cec658-c920-4aae-e6b2-08df3c2152a3 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: MAD0EPF000008B4.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZR6PR10MB992253 This series updates the STM32MP25 RCC bindings and clock driver: - Patch 1 makes the driver define the number of clocks of its provider (STM32MP25_LAST_CLK) instead of taking it from the binding header, and drops it from that header. That value is not part of the binding ABI and would have to change each time an ID is added. This is already how the STM32MP21 clock driver does it. No functional change. The driver and the header are changed by the same patch, as the macro has the same name in both. The driver patches 5 and 7 then update the number of clocks. - Patches 2-3 add the kernel clocks of the ETR and STM, and rename the RCC_STMCFGR register (driver internal) to match the reference manual. - Patches 4-5 add the clocks to allocate the D3 peripherals to the Cortex-M0 (CPU3) and to enable their autonomous mode. The binding patch also adds the HSI, HSE and MSI kernel clocks as three new RCC input clocks. They are optional (minItems), so that the existing device trees remain valid. - Patches 6-7 add the ck_ker_usb2phy1_stp clock needed by USB host low power support, with the HSE kernel clock introduced by patch 5 as parent to keep it running in low power modes. - Patch 8 uses the reference manual names for the bus clocks of the ETR and STM (CK_BUS_STM, CK_SCMI_BUS_ETR and CK_SCMI_BUS_STM), consistent with their new kernel clocks and with the STM32MP21 binding. The values are unchanged and the old names are kept as deprecated aliases, so existing users are not affected. It is the last patch so that it can be dropped independently. The patches are kept in one series because the binding identifiers are allocated sequentially in the same header, and patch 7 uses the HSE kernel clock parent added by patch 5. Signed-off-by: Gabriel Fernandez --- Changes in v4: - Patch 5: fix the commit message, the MSI KER clock is the parent of the CPU3 allocation clocks (GATE_C3), not of the autonomous mode clocks (GATE_AM). Reported by the Sashiko AI review. No code change. - Link to v3: https://lore.kernel.org/r/20261106-ups_mp25_clk_update-v3-0-4a32f68119ed@foss.st.com Changes in v3: - Patch 2: only add the kernel clocks, do not rename the existing bus clock identifiers anymore (Krzysztof). - New patch 8: use the reference manual names for the ETR and STM bus clocks and keep the old names as deprecated aliases, so that existing users are not affected (Krzysztof). - Patches 4 and 6: drop the redundant "binding" from the subject (Krzysztof). - Patch 5: keep GATE_RTCC3 after GATE_RNG in stm32mp25_gates[], as in enum_gate_cfg (Brian). - Patches 1 and 6: add Acked-by from Krzysztof. - Link to v2: https://lore.kernel.org/r/20261023-ups_mp25_clk_update-v2-0-398d348ea8fd@foss.st.com Changes in v2: - Patch 7: drop the custom clock ops and the recalc_rate reading ck_ker_usb2phy1, and use clk_stm32_gate_ops directly. This fixes the missing .disable_unused (gate counter underflow in clk_disable_unused()) and the stale cached rate, as the rate is now derived by the CCF from the real parent. Both reported by the Sashiko AI review. - Patch 7: update the commit message accordingly. - Other patches are unchanged. - Link to v1: https://lore.kernel.org/r/20261023-ups_mp25_clk_update-v1-0-e906e7a38cb3@foss.st.com --- Gabriel Fernandez (7): clk: stm32mp25: define the number of clocks in the driver dt-bindings: stm32: add kernel clocks for ETR and STM clk: stm32mp25: update register with reference manual clk: stm32mp25: add clock for D3 peripherals allocation for Cortex-CM0 dt-bindings: stm32: add usb2phy1stp clock on stm32mp25 clk: stm32mp25: add ck_ker_usb2phy1_stp clock dt-bindings: stm32: use reference manual names for ETR and STM bus clocks Gwenael Treuveur (1): dt-bindings: stm32: add clocks for Cortex-CM0 on stm32mp25 .../bindings/clock/st,stm32mp25-rcc.yaml | 9 +- drivers/clk/stm32/clk-stm32mp25.c | 187 +++++++++++++++++++++ drivers/clk/stm32/stm32mp25_rcc.h | 2 +- include/dt-bindings/clock/st,stm32mp25-rcc.h | 53 +++++- 4 files changed, 244 insertions(+), 7 deletions(-) --- base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a change-id: 20261022-ups_mp25_clk_update-7f1a03b1c6f2 Best regards, -- Gabriel Fernandez