From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=209.85.210.70 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793925786; b=yu9djr51eH0ldBbFdE4csvMopz7yzRz9fY0s/TwlX9Nz66HxwS8ei/y73kK7mCrl9NqM mzQ0q2YF6r5z8H3Vxs/1vvvQsGslDcOnrota0n6lMwCNDQbXbvO4o1fn/OrddJqNAdtZs RNgLUfB5BCYn2XlQlpXgQiIqqiw+s5jFQWEWTtLhdalECLu16o4DX+XxkYNhi0uFe52Jt lE54oqe7d8mAORRS9bLfYynG+Jm4qzZfqdQ/lI1Pq0UmLxTK0E8YXuekNiIoslHOTCLHd aj/wmtiuEwVoDRuQqMi4e6I0HFFphaDc2dQMIXnoJ7A6hLvh2I87U5XwQONkmYbbRLQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793925786; h=DMARC-Filter:Received:DKIM-Signature:X-Google-DKIM-Signature: X-Forwarded-Encrypted:X-Gm-Message-State:X-Received:Date:In-Reply-To: Mime-Version:References:X-Mailer:Message-ID:Subject:From:To:Cc: Content-Type; bh=ddBqCr/aEaadxkJlxFoZmLz139RBeJBOYwKmQVBOEIY=; b=zE2cZvmXp0hnEWBndmYnodhBjIdQ1A6EvfjWJGcsSpz7zYNTUCcRKwND0oRmtUccHj9Y ZVnafp5yeTJdJKtn2N0+fyy4kgH6jYKMJiFYBfMfc+iOF/KMA3cE3YGZHlr1ll/qGNH5Y qqaUDfwea3xjhSo6pWYbtjonhNwfaXoBSUFAO8Oy1hRKqo2I3xuT9eCArxVthwyNKp5n2 NgjOPJIjoYboUUiqgiNaUqzGr6CcFePG7miLYmypM1zPJHXFVn6gN7lPW2RxnXOgakF8T IRR8psesWLcO5diLUFxFS+PPwPQ/C/lD3XpMwR2DsecHZIExn3TIZdwiyuUwsC6i27g== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=google.com; spf=pass smtp.mailfrom=flex--dmatlack.bounces.google.com; dkim=pass header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20260707 header.b=GRXD3J3V; arc=none smtp.remote-ip=209.85.210.70 Received: from mail-ot1-f70.google.com (mail-ot1-f70.google.com [209.85.210.70]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EA10606D837 for ; Fri, 6 Nov 2026 00:43:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 7EA10606D837 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--dmatlack.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20260707 header.b=GRXD3J3V Received: by mail-ot1-f70.google.com with SMTP id 46e09a7af769-84478a97bfbso331784a34.0 for ; Thu, 05 Nov 2026 16:43:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20260707; t=1793925785; x=1794530585; darn=vger.kernel.org; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ddBqCr/aEaadxkJlxFoZmLz139RBeJBOYwKmQVBOEIY=; b=GRXD3J3VOcw4yv/Vrvlmc3RGpi31lT5MppCPnPUi/kZ6+en1QhpIi/gHunKi3NU+7D I41HoHyhAjHakKs6kVhSRTfJh1vxqz9vVp55WuHs5Fn5aoEb9Nu8eWmHE10+gUaG7UiG 5mvzx296xi4VXPJipSajDJSuQfy21T18LyYHbTT1tpI7JrwxYMHYmX27+hmjwhH/x5rH g3wSNZ9BqAGqF+GJsOMtmfLprgg5yjVMsfHI5WkuHVOYbBpmloYhRA7cOjlsUUp855Av OJf+YqG+dK+3au2b3skaY9vPuLF92rpVe8BjWCJqSPGWBf4iKLMycdhtEKJXZVGCAuzT dC7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1793925785; x=1794530585; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ddBqCr/aEaadxkJlxFoZmLz139RBeJBOYwKmQVBOEIY=; b=aXtVE2Ln/Ds2VB+lwebUW3nUdi2g+JoQG44g8dVii4On5GXoPASFMOKP05DeMCV/se yza6u6UajXeyHwN9DFcWacTWfcxSQB4FxuuFUof7aVI6z+JtI/Wz4nG1DmggnD4kPjJj 4CBEEF+j/kfsGHh2jiRJQFvnPl2m2dMjOoGqmsUzo4SSVuYEKLRb72s275jJLcWUPFnB lOlpe2FY/O8rWvDBKe3Ws4bZmoooHZ/SrDhmgVLKSfh33pJTrdQfOJVeMewmdnlN3sPX 4il1PYdvV1UpKJFSbnSFf5ypAD/GWmpGiKhDs2iMk5yjXjB//zaLGHIKMRJUbIkv3MJ4 wvVA== X-Forwarded-Encrypted: i=1; AKwUvByATMVMegm52p+AF9WhNA1lHarxQyw/z7mkNeNuJVVW7l4qEE6biDFmLEFzpeqnrlZQBTwlGsC4NDXI41U=@vger.kernel.org X-Gm-Message-State: APuU4Z/G141194Qtm2zbDriwl8dhkQFvzylcOMeCzEB0gPP3bDJrN9PH 4LKIe9PyjwNmhi+O1KQ8XdB/PKvQYssXpdSZWJng3IAKnSxW/XYBMBls3JZNQ+LmqqoN3Tsa8mJ zg3rUKTI+mljyoQ== X-Received: from iobmm23-n1.prod.google.com ([2002:a05:6602:7117:10b0:9ca:dec8:c75d]) (user=dmatlack job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6808:1987:b0:4f3:68d6:f131 with SMTP id 5614622812f47-567e099488cmr858385b6e.2.1793925785214; Thu, 05 Nov 2026 16:43:05 -0800 (PST) Date: Fri, 6 Nov 2026 00:42:08 +0000 In-Reply-To: <20261106004218.604799-1-dmatlack@google.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Mime-Version: 1.0 References: <20261106004218.604799-1-dmatlack@google.com> X-Mailer: git-send-email 2.56.0.455.g6c5a503b38-goog Message-ID: <20261106004218.604799-8-dmatlack@google.com> Subject: [PATCH v2 07/17] PCI/ASPM: Save L1SS state in the saved capability store From: David Matlack To: kexec@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: Alexander Graf , Alex Williamson , Bjorn Helgaas , David Matlack , Jason Gunthorpe , Jonathan Corbet , Josh Hilke , Lukas Wunner , Mahesh J Salgaonkar , Mike Rapoport , "Oliver O'Halloran" , Pasha Tatashin , Pratyush Yadav , Randy Dunlap , Samiullah Khawaja , Shuah Khan , Vipin Sharma Content-Type: text/plain; charset="UTF-8" Save and restore the L1 PM Substates control registers through the per-device saved capability store instead of a private pci_cap_saved_state buffer. pci_restore_aspm_l1ss_state() needs both the Upstream and Downstream Port's saved L1SS configuration, and had to fetch two buffers and decode each by index. Read the saved values by configuration space offset instead, which names the register at every use. Add pci_read_saved_l1ss_ctl() to read one device's pair, so that the Port and the device below it are read the same way. Reserve PCI_L1SS_CTL1 and PCI_L1SS_CTL2 with a single request in pci_reserve_aspm_l1ss_state(), since they are adjacent DWORDs. Skip the reservation when the device has no L1SS capability, which pci_add_ext_cap_save_buffer() did implicitly. No functional change intended. Signed-off-by: David Matlack --- drivers/pci/pcie/aspm.c | 63 ++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 33 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 39adf2cad331..2978fde87af6 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -68,24 +68,29 @@ void pci_restore_ltr_state(struct pci_dev *dev) pci_restore_cap_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT); } -void pci_configure_aspm_l1ss(struct pci_dev *pdev) +static void pci_reserve_aspm_l1ss_state(struct pci_dev *pdev) { int rc; - pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - - rc = pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_L1SS, - 2 * sizeof(u32)); + /* PCI_L1SS_CTL1 and PCI_L1SS_CTL2 are adjacent DWORDs */ + rc = pci_reserve_saved_cap(pdev, pdev->l1ss + PCI_L1SS_CTL1, 2 * sizeof(u32)); if (rc) - pci_err(pdev, "unable to allocate ASPM L1SS save buffer (%pe)\n", + pci_err(pdev, "unable to reserve ASPM L1SS save state (%pe)\n", ERR_PTR(rc)); } +void pci_configure_aspm_l1ss(struct pci_dev *pdev) +{ + pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); + if (!pdev->l1ss) + return; + + pci_reserve_aspm_l1ss_state(pdev); +} + void pci_save_aspm_l1ss_state(struct pci_dev *pdev) { struct pci_dev *parent = pdev->bus->self; - struct pci_cap_saved_state *save_state; - u32 *cap; /* * If this is a Downstream Port, we never restore the L1SS state @@ -102,32 +107,32 @@ void pci_save_aspm_l1ss_state(struct pci_dev *pdev) * Save L1 substate configuration. The ASPM L0s/L1 configuration * in PCI_EXP_LNKCTL_ASPMC is saved by pci_save_pcie_state(). */ - save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS); - if (!save_state) - return; - - cap = &save_state->cap.data[0]; - pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cap++); - pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cap++); + pci_save_cap_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2); + pci_save_cap_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1); /* * Save parent's L1 substate configuration so we have it for * pci_restore_aspm_l1ss_state(pdev) to restore. */ - save_state = pci_find_saved_ext_cap(parent, PCI_EXT_CAP_ID_L1SS); - if (!save_state) - return; + pci_save_cap_dword(parent, parent->l1ss + PCI_L1SS_CTL2); + pci_save_cap_dword(parent, parent->l1ss + PCI_L1SS_CTL1); +} - cap = &save_state->cap.data[0]; - pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, cap++); - pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, cap++); +/* + * Read a device's saved L1 substate configuration. + * + * Return: true if both registers had a saved value, false otherwise. + */ +static bool pci_read_saved_l1ss_ctl(struct pci_dev *dev, u32 *ctl1, u32 *ctl2) +{ + return pci_read_saved_cap_dword(dev, dev->l1ss + PCI_L1SS_CTL1, ctl1) && + pci_read_saved_cap_dword(dev, dev->l1ss + PCI_L1SS_CTL2, ctl2); } void pci_restore_aspm_l1ss_state(struct pci_dev *pdev) { - struct pci_cap_saved_state *pl_save_state, *cl_save_state; struct pci_dev *parent = pdev->bus->self; - u32 *cap, pl_ctl1, pl_ctl2, pl_l1_2_enable; + u32 pl_ctl1, pl_ctl2, pl_l1_2_enable; u32 cl_ctl1, cl_ctl2, cl_l1_2_enable; u16 clnkctl, plnkctl; @@ -142,18 +147,10 @@ void pci_restore_aspm_l1ss_state(struct pci_dev *pdev) if (!pdev->l1ss || !parent->l1ss) return; - cl_save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS); - pl_save_state = pci_find_saved_ext_cap(parent, PCI_EXT_CAP_ID_L1SS); - if (!cl_save_state || !pl_save_state) + if (!pci_read_saved_l1ss_ctl(pdev, &cl_ctl1, &cl_ctl2) || + !pci_read_saved_l1ss_ctl(parent, &pl_ctl1, &pl_ctl2)) return; - cap = &cl_save_state->cap.data[0]; - cl_ctl2 = *cap++; - cl_ctl1 = *cap; - cap = &pl_save_state->cap.data[0]; - pl_ctl2 = *cap++; - pl_ctl1 = *cap; - /* Make sure L0s/L1 are disabled before updating L1SS config */ pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &clnkctl); pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &plnkctl); -- 2.56.0.455.g6c5a503b38-goog