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Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000C8.mail.protection.outlook.com (10.167.240.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.615.4 via Frontend Transport; Fri, 6 Nov 2026 01:34:54 +0000 Received: from ubuntu (unknown [172.20.64.99]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 628084102E60; Fri, 6 Nov 2026 09:34:53 +0800 (CST) From: Jelly Jia To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.murphy@arm.com Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org, cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com Subject: [PATCH v6 0/5] dmaengine: arm-dma350: Add slave support and Sky1 integration Date: Fri, 6 Nov 2026 09:34:48 +0800 Message-ID: <20261106013453.1134239-1-Jelly.Jia@cixtech.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C8:EE_|TYPPR06MB8328:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: c73f0f13-3278-4f9a-e5db-08df3ba628e7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|1800799024|376014|7416014|261009223027099003|261028144727099003|261026121527099003|261102123227099003|261022105027099003|261022075727099003|56012099006|261021123027099003|261026140227099003|261021121427099003|3023799007|6133799003|10067099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gMi3nlYCDWL6Pvg+zdCQ5msgZB9CGod5XBQ7arm73yrIOWbAXH7s8SBNW6zzLLFYx9E1wSUYKkn+y9Gb8xb387aK5PyjSDkF01/srBQGQ17r+xJ0NtqYSR1pjpFGXcoB3QgzI/eMV1KQTF1INlAW2eJR1sBQ4ckLUBU0/k8mwaE3LBhpB58nwMWmgAJRgq9mcxvgItxDb2y8D1cwMupylW7gXUUwxal3D+9L7+HQX+YYGup+SDRl8UrOq/eF2CzUiCbQAJsArb+cR+8IA1yUGK5bag/SJmiW9azlkUE53OLS2Jrgbh60l88t1r66ximHaYDThRbFTprKvcpFvegi9Xi7367lgWAI9EtfIiLSF83+VdvT8ojaau62Ed7HJGKldHvrbJ+zU2REmMzDx1FCHV3wBZ12hFn3LlvhZPUcoOXw+nIjMv0f/p/1kRpMV4sz X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 01:34:54.4572 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c73f0f13-3278-4f9a-e5db-08df3ba628e7 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C8.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYPPR06MB8328 Hello, This series adds scatter-gather and cyclic slave transfer support to the Arm DMA-350 driver, then describes the clock, reset and DMA address view of the CIX Sky1 FCH integration. Patch 1 fixes the source-trigger bit. Patch 2 adds peripheral transfers with descriptor-owned resource mappings, coherent linked commands and hardware-based residue reporting. Patches 3 and 4 describe and handle integration clocks and resets. Patch 5 describes the FCH DMA address windows and adds its bus clock. Sky1 controller nodes use cix,sky1-dma350 with an arm,dma-350 fallback. The binding requires a bus clock for Sky1 and leaves its reset optional; both resources remain optional for the generic compatible alone. The driver uses standard optional resource helpers and introduces no CIX-specific register programming. The companion AUDSS interrupt-path series builds on this one and manages the AUDSS interrupt gates in the CRU driver. Changes since v5: - Add the Sky1 compatible with a generic fallback and require clocks for Sky1 only. Keep resets optional and update the FCH node. (Frank.) - Initialize the request to an invalid sentinel and clear request/config state when channel resources are freed, but retain it across terminate. (Sashiko, followed up by Frank.) - Keep a failed channel in DMA_ERROR until termination, preventing queued work from overwriting the failed cookie's status and residue. Allow terminate to clear the error without an active descriptor. (Sashiko, followed up by Frank.) - Add Frank's Reviewed-by to the unchanged clock/reset driver patch. Previous version: https://lore.kernel.org/r/20261104124411.296640-1-Jelly.Jia@cixtech.com Jelly Jia (5): dmaengine: arm-dma350: Fix source trigger bit dmaengine: arm-dma350: Add slave and cyclic transfer support dt-bindings: dma: arm,dma-350: Describe the CIX Sky1 integration dmaengine: arm-dma350: Support integration clocks and resets arm64: dts: cix: Describe the Sky1 FCH DMA-350 integration .../devicetree/bindings/dma/arm,dma-350.yaml | 30 +- arch/arm64/boot/dts/cix/sky1.dtsi | 36 +- drivers/dma/arm-dma350.c | 837 +++++++++++++++++- 3 files changed, 856 insertions(+), 47 deletions(-) base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.54.0