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Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000C7.mail.protection.outlook.com (10.167.240.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.615.4 via Frontend Transport; Fri, 6 Nov 2026 01:35:22 +0000 Received: from ubuntu (unknown [172.20.64.99]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 2539E4102E68; Fri, 6 Nov 2026 09:35:21 +0800 (CST) From: Jelly Jia To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.murphy@arm.com, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org, cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com, linux-clk@vger.kernel.org, joakim.zhang@cixtech.com Subject: [PATCH v3 1/5] dt-bindings: soc: cix: Describe the Sky1 AUDSS DMA IRQ controller Date: Fri, 6 Nov 2026 09:35:16 +0800 Message-ID: <20261106013520.1134450-2-Jelly.Jia@cixtech.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261106013520.1134450-1-Jelly.Jia@cixtech.com> References: <20261106013520.1134450-1-Jelly.Jia@cixtech.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C7:EE_|KUXPR06MB9059:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 9e0913fd-1a7c-4109-94e4-08df3ba63981 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|1800799024|376014|7416014|261009223027099003|261028144727099003|261026121527099003|261102123227099003|261022105027099003|56012099006|261021123027099003|261026140227099003|261021121427099003|6133799003|10067099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sLkoCad3blkLvzM+0TL1BLK5tDet9RqRXRv0AWZ3Pylf1vgL/16ZoCkHGMRHPJjdIGDUUCXhSxFqavGDk3Qu2WkKrsvQFJ9Jdg/7jhaianwtAH0/73CDOFMFRI3N7CvQ5/UvwQ0a/e8CBNK5ZXjdLn6QnDnsF4AtGaL2lrMNZ0dlEfap4o4Q8FtVoawBQ+G4NOM8Ftrn1FthWaAa1dKE7OmQhnDB+0W5IGfRMwURrSAkmqWS8MH3KxoZu0e+JaboQgWeLpKcTlwFl9eWbsf5DbeANRlhzjihrNy5QuJYVhkmy/EV61mTihSHtVjmx5uTvwrCqOLW0f1I8dXhEHZgWLE/Onsmr1nO4QCPOAL9KFtippxtRDmdjpTgOHwbCghqoK3IrjvjAf7hrpQ1D3pi7QBP+4EAcHGQza3qw+tk0i+zzafM1RdNiyZzCJTYDHR0 X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 01:35:22.3026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e0913fd-1a7c-4109-94e4-08df3ba63981 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C7.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KUXPR06MB9059 The AUDSS CRU contains a separate AP interrupt gate for each of the eight DMA-350 channels. The enabled inputs are combined onto one GIC interrupt. These gates are part of the CRU register block, not the DMA controller. Describe the CRU as an interrupt-controller in addition to its clock and reset functions. A child interrupt specifier contains the DMA channel index, matching the corresponding gate bit; the parent interrupt is the combined GIC line. Signed-off-by: Jelly Jia --- .../bindings/soc/cix/cix,sky1-audss-cru.yaml | 37 ++++++++++++++++++- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml index 50dd0593e1d9..aa0c557abec0 100644 --- a/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml @@ -28,6 +28,12 @@ description: | The SoC syscon NoC (or bus) reset is described via resets. The audio subsystem power domain is described via power-domains. + The same register block contains the eight DMA-350 channel interrupt + gates at offset 0x54. When the node is an interrupt-controller, the + cell is the DMA channel index (0 through 7). The corresponding gate + bit is unmasked while that interrupt is requested, and the eight + inputs are combined onto the parent GIC interrupt. + properties: compatible: const: cix,sky1-audss-cru @@ -45,6 +51,18 @@ properties: description: Reset indices are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h. + interrupt-controller: true + + '#interrupt-cells': + const: 1 + description: + The cell is the DMA-350 channel index, 0 through 7. + + interrupts: + maxItems: 1 + description: + Combined DMA-350 channel interrupt after the CRU gates. + clocks: items: - description: I2S parent clock for sampling rates multiple of 8kHz. @@ -75,18 +93,33 @@ required: - power-domains - resets +allOf: + - if: + required: + - interrupt-controller + then: + required: + - '#interrupt-cells' + - interrupts + additionalProperties: false examples: - | - audss_cru: clock-controller@7110000 { + #include + #include + + clock-controller@7110000 { compatible = "cix,sky1-audss-cru"; reg = <0x7110000 0x10000>; #clock-cells = <1>; - #reset-cells = <1>; clocks = <&scmi_clk 76>, <&scmi_clk 78>, <&scmi_clk 70>, <&scmi_clk 71>; clock-names = "x8k", "x11k", "sys", "48m"; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = ; power-domains = <&smc_devpd 0>; + #reset-cells = <1>; resets = <&s5_syscon 31>; }; -- 2.54.0