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From: Zide Chen <zide.chen@intel.com>
To: Sean Christopherson <seanjc@google.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Peter Zijlstra <peterz@infradead.org>
Cc: kvm@vger.kernel.org, Jim Mattson <jmattson@google.com>,
	Yosry Ahmed <yosry@kernel.org>, Andi Kleen <ak@linux.intel.com>,
	Stephane Eranian <eranian@google.com>,
	linux-kernel@vger.kernel.org, Mingwei Zhang <mizhang@google.com>,
	Zide Chen <zide.chen@intel.com>,
	Das Sandipan <Sandipan.Das@amd.com>,
	Shukla Manali <Manali.Shukla@amd.com>,
	Dapeng Mi <dapeng1.mi@linux.intel.com>,
	Xudong Hao <xudong.hao@intel.com>
Subject: [PATCH v3 16/18] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is set
Date: Thu,  5 Nov 2026 18:39:25 -0700	[thread overview]
Message-ID: <20261106013927.166209-17-zide.chen@intel.com> (raw)
In-Reply-To: <20261106013927.166209-1-zide.chen@intel.com>

Intel PerfMon v5 introduces the ANYTHREAD_DEPRECATION capability
(CPUID.0AH:EDX[15]) to indicate that AnyThread counting is deprecated
and that writes to the AnyThread bit in IA32_PERFEVTSELx and
IA32_FIXED_CTR_CTRL are ignored.

Preserve the guest-written value in guest-visible state so that guest
RDMSRs observe the AnyThread bit, but strip it before programming
hardware to ensure cross-VM SMT isolation.

Continue to inject #GP when ANYTHREAD_DEPRECATION is not present in the
guest CPUID, e.g. for PerfMon v3/v4 guests or when the capability is
not configured for a PerfMon v5+ guest.

Advertise CPUID.0AH:EDX[15] only for PMU version 5+ guests, since the
bit doesn't exist below version 5.

Signed-off-by: Zide Chen <zide.chen@intel.com>
---
v3:
- Exclude Fixed Counter 3 bit 14 (METRICS_CLEAR_EN) from the AnyThread mask
  so it remains reserved in fixed_ctr_ctrl_rsvd. (Jim)
- Preserve AnyThread in guest-visible state (eventsel/fixed_ctr_ctrl) to
  match bare-metal RDMSR behavior. (Jim)
- Removed it from the hardware-visible counterparts (_hw) so that it
  doesn't need to explicitly remove this bit in intel_pmu_set_msr().
  (Jim)
- Re-use intel_pmu_fixed_ctrl_bits() for AnyThread bits computation.
  (Sashiko)

v2:
- Advertise anythread_deprecated only if kvm_pmu_cap.version >= 5.
- Add the missing AnyThr bit handling for IA32_FIXED_CTR_CTRL.
- Update the comments to be clearer.
---
 arch/x86/kvm/cpuid.c         |  2 +-
 arch/x86/kvm/vmx/pmu_intel.c | 28 +++++++++++++++++++++++++---
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 00a2ca6d3049..66e68a867946 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1549,7 +1549,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 					    KVM_MAX_NR_FIXED_COUNTERS);
 		edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
 
-		if (kvm_pmu_cap.version)
+		if (kvm_pmu_cap.version >= 5)
 			edx.split.anythread_deprecated = 1;
 
 		entry->eax = eax.full;
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 6bd7c8e03c14..961d16e7f31f 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -67,6 +67,13 @@ static u64 intel_pmu_fixed_ctrl_bits(struct kvm_pmu *pmu, u64 bits)
 	return fixed_ctrl_bits;
 }
 
+static u64 intel_pmu_fixed_anythread_mask(struct kvm_pmu *pmu)
+{
+	/* Fixed counter 3 repurposes that bit for METRICS_CLEAR_EN. */
+	return intel_pmu_fixed_ctrl_bits(pmu, INTEL_FIXED_0_ANYTHREAD) &
+	       ~intel_fixed_bits_by_idx(3, INTEL_FIXED_3_METRICS_CLEAR);
+}
+
 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
 {
 	/*
@@ -83,9 +90,9 @@ static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
 	int i;
 
 	pmu->fixed_ctr_ctrl = data;
-	pmu->fixed_ctr_ctrl_hw = data;
+	pmu->fixed_ctr_ctrl_hw = data & ~intel_pmu_fixed_anythread_mask(pmu);
 	kvm_for_each_fixed_counter(i, fixed_mask) {
-		u8 new_ctrl = fixed_ctrl_field(data, i);
+		u8 new_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl_hw, i);
 		u8 old_ctrl = fixed_ctrl_field(old_fixed_ctr_ctrl, i);
 
 		if (old_ctrl == new_ctrl)
@@ -500,7 +507,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 
 			if (data != pmc->eventsel) {
 				pmc->eventsel = data;
-				pmc->eventsel_hw = data;
+				pmc->eventsel_hw = data & ~ARCH_PERFMON_EVENTSEL_ANY;
 				kvm_pmu_request_counter_reprogram(pmc);
 			}
 			break;
@@ -672,6 +679,21 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 
 	pmu->fixed_ctr_ctrl_rsvd &=
 		~intel_pmu_fixed_ctrl_bits(pmu, fixed_enable_bits);
+
+	/*
+	 * AnyThread counting is not supported by KVM due to cross-VM
+	 * information leakage concerns on SMT cores. Therefore, AnyThread
+	 * remains unavailable for PerfMon v3/v4 guests, where AnyThread
+	 * deprecation is not enumerated.
+	 *
+	 * On PerfMon v5+ with ANYTHREAD_DEPRECATION, writes to AnyThread bits
+	 * are accepted and preserved on RDMSR, while counting behavior is
+	 * ignored.
+	 */
+	if (pmu->version >= 5 && edx.split.anythread_deprecated) {
+		pmu->eventsel_rsvd &= ~ARCH_PERFMON_EVENTSEL_ANY;
+		pmu->fixed_ctr_ctrl_rsvd &= ~intel_pmu_fixed_anythread_mask(pmu);
+	}
 }
 
 static void intel_pmu_init(struct kvm_vcpu *vcpu)
-- 
2.56.0


  parent reply	other threads:[~2026-11-06  1:50 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-06  1:39 [PATCH v3 00/18] KVM: x86/pmu: Add mediated vPMU PerfMon v5 support Zide Chen
2026-11-06  1:39 ` [PATCH v3 01/18] KVM: x86/pmu: Remove redundant Perf Global Status MSR bit definitions Zide Chen
2026-11-06  1:39 ` [PATCH v3 02/18] KVM: x86/pmu: Rename all_valid_pmc_idx to pmc_exists Zide Chen
2026-11-06  1:39 ` [PATCH v3 03/18] KVM: x86/pmu: Rename reserved_bits to eventsel_rsvd in kvm_pmu Zide Chen
2026-11-06  1:39 ` [PATCH v3 04/18] KVM: x86/pmu: Add PMC bitmap accessor helpers Zide Chen
2026-11-06  1:39 ` [PATCH v3 05/18] KVM: x86/pmu: Drop nr_arch_{gp,fixed}_counters from kvm_pmu Zide Chen
2026-11-06  1:39 ` [PATCH v3 06/18] KVM: x86/pmu: Expose kvm_host_pmu to vendor modules Zide Chen
2026-11-06  1:39 ` [PATCH v3 07/18] perf/x86: Plumb counter bitmap from x86_pmu to x86_pmu_cap Zide Chen
2026-11-06  1:39 ` [PATCH v3 08/18] KVM: x86/pmu: Switch to bitmask-based KVM PMU capabilities Zide Chen
2026-11-06  1:39 ` [PATCH v3 09/18] perf/x86: Remove num_counters_{gp,fixed} from x86_pmu_capability Zide Chen
2026-11-06  1:39 ` [PATCH v3 10/18] KVM: x86/pmu: Document GLOBAL_STATUS_RESET passthrough erratum Zide Chen
2026-11-06  1:39 ` [PATCH v3 11/18] KVM: x86/pmu: Emulate IA32_PERF_GLOBAL_STATUS_SET MSR Zide Chen
2026-11-06  1:39 ` [PATCH v3 12/18] KVM: x86/pmu: Emulate IA32_PERF_GLOBAL_INUSE MSR Zide Chen
2026-11-06  1:39 ` [PATCH v3 13/18] KVM: x86/pmu: Populate CPUID.0AH:ECX fixed-counter bitmap Zide Chen
2026-11-06  1:39 ` [PATCH v3 14/18] KVM: x86/pmu: Factor out fixed counter control bit calculation Zide Chen
2026-11-06  1:39 ` [PATCH v3 15/18] KVM: x86/pmu: Mask only OS/USR bits when filtering fixed counters Zide Chen
2026-11-06  1:39 ` Zide Chen [this message]
2026-11-06  1:39 ` [PATCH v3 17/18] KVM: x86/pmu: Advertise PerfMon version 5 on Intel hosts Zide Chen
2026-11-06  1:39 ` [PATCH v3 18/18] KVM: selftests: Support fixed counters bitmap in pmu_counters_test Zide Chen

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