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Rename it to eventsel_rsvd to better reflect its purpose and to align with other field names in struct kvm_pmu. Opportunistically, replace magic numbers with macros. No functional change intended. Suggested-by: Dapeng Mi Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi Reviewed-by: Jim Mattson Reviewed-by: Sandipan Das --- v3: - Mention "magic numbers" in changelog to cover AMD as well. v2: - Replace magic numbers in AMD pmu->eventsel_rsvd. --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/pmu.c | 6 +++++- arch/x86/kvm/svm/pmu.c | 12 +++++++++--- arch/x86/kvm/vmx/pmu_intel.c | 12 ++++++------ 4 files changed, 21 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 72b8fbf432a2..b8875ed5502c 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -581,7 +581,7 @@ struct kvm_pmu { u64 counter_bitmask[2]; u64 global_ctrl_rsvd; u64 global_status_rsvd; - u64 reserved_bits; + u64 eventsel_rsvd; u64 raw_event_mask; struct kvm_pmc gp_counters[KVM_MAX_NR_GP_COUNTERS]; struct kvm_pmc fixed_counters[KVM_MAX_NR_FIXED_COUNTERS]; diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 83883191d124..cbd63329cf13 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -983,7 +983,11 @@ void kvm_pmu_refresh(struct kvm_vcpu *vcpu) pmu->nr_arch_fixed_counters = 0; pmu->counter_bitmask[KVM_PMC_GP] = 0; pmu->counter_bitmask[KVM_PMC_FIXED] = 0; - pmu->reserved_bits = 0xffffffff00200000ull; + /* + * KVM is not able to emulate the AnyThread bit due to cross-VM + * information leakage on SMT cores. + */ + pmu->eventsel_rsvd = GENMASK_ULL(63, 32) | ARCH_PERFMON_EVENTSEL_ANY; pmu->raw_event_mask = X86_RAW_EVENT_MASK; pmu->global_ctrl_rsvd = ~0ull; pmu->global_status_rsvd = ~0ull; diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index c18286545a7a..52224872e0d4 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -163,7 +163,7 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) /* MSR_EVNTSELn */ pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL); if (pmc) { - data &= ~pmu->reserved_bits; + data &= ~pmu->eventsel_rsvd; if (data != pmc->eventsel) { pmc->eventsel = data; pmc->eventsel_hw = (data & ~AMD64_EVENTSEL_HOSTONLY) | @@ -214,9 +214,15 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1; - pmu->reserved_bits = 0xfffffff000280000ull; + /* + * AMD PerfEvtSeln registers do not support PinControl, and KVM does + * not emulate AnyThread due to cross-VM information leakage on SMT + * cores (as on the Intel side). + */ + pmu->eventsel_rsvd = GENMASK_ULL(63, 36) | ARCH_PERFMON_EVENTSEL_PIN_CONTROL | + ARCH_PERFMON_EVENTSEL_ANY; if (guest_cpu_cap_has(vcpu, X86_FEATURE_SVM) && kvm_vcpu_has_mediated_pmu(vcpu)) - pmu->reserved_bits &= ~AMD64_EVENTSEL_HOST_GUEST_MASK; + pmu->eventsel_rsvd &= ~AMD64_EVENTSEL_HOST_GUEST_MASK; pmu->raw_event_mask = AMD64_RAW_EVENT_MASK; /* not applicable to AMD; but clean them to prevent any fall out */ diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index ee18899614a1..fadc466cd600 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -388,7 +388,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) struct kvm_pmc *pmc; u32 msr = msr_info->index; u64 data = msr_info->data; - u64 reserved_bits, diff; + u64 eventsel_rsvd, diff; switch (msr) { case MSR_CORE_PERF_FIXED_CTR_CTRL: @@ -436,11 +436,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) pmc_write_counter(pmc, data); break; } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { - reserved_bits = pmu->reserved_bits; + eventsel_rsvd = pmu->eventsel_rsvd; if ((pmc->idx == 2) && (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED)) - reserved_bits ^= HSW_IN_TX_CHECKPOINTED; - if (data & reserved_bits) + eventsel_rsvd ^= HSW_IN_TX_CHECKPOINTED; + if (data & eventsel_rsvd) return 1; if (data != pmc->eventsel) { @@ -548,7 +548,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) if (entry && (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) && (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM))) { - pmu->reserved_bits ^= HSW_IN_TX; + pmu->eventsel_rsvd ^= HSW_IN_TX; pmu->raw_event_mask |= (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); } @@ -587,7 +587,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) if (perf_capabilities & PERF_CAP_PEBS_FORMAT) { if (perf_capabilities & PERF_CAP_PEBS_BASELINE) { pmu->pebs_enable_rsvd = counter_rsvd; - pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; + pmu->eventsel_rsvd &= ~ICL_EVENTSEL_ADAPTIVE; pmu->pebs_data_cfg_rsvd = ~0xff00000full; intel_pmu_enable_fixed_counter_bits(pmu, ICL_FIXED_0_ADAPTIVE); } else { -- 2.56.0