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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36fa9ed126csm1484905eec.18.2026.11.05.19.02.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 19:02:16 -0800 (PST) From: Anusha Arun Nandi To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: Abel Vesa , gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] arm64: dts: qcom: kodiak: add CSI2 D-PHY common-phy providers Date: Thu, 5 Nov 2026 19:02:12 -0800 Message-Id: <20261106030212.2811027-4-anusha.nandi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261106030212.2811027-1-anusha.nandi@oss.qualcomm.com> References: <20261106030212.2811027-1-anusha.nandi@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 028Prj-d0QX_Ct5S-9hT16ZUKmVkrPTv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDAxMSBTYWx0ZWRfX/esdnJZWlYZw i+7FcM89fu/V9iEtp+mDEugcNFKnWFQXSv0MCfmmAImB5FIMciXv20zSWIQUg6EsxouMBz6sHWk JVlOf+EuGbLH8fpYGEtkydML+F8sSWz4eQ5L7W2fDg90qWFbeVNxgVIN1eSAS0opaPIag2gj6zu 3qlBxIV9yMWCqM/Q12CQHVDUSuvlDSi+iOnnbM8gWIlln05GH6n9Lcvq6/SV0/eL4JxkUppkirk iZKQryKxeVsOW3P1q8I/VEPorgaeWijfN5Ewqf9BngbixeJ0Xf3Gnx+/SJ1Cr/hyRMx8d+/YL3G UurfQS0daDIMibeZfNgeNw/p5iXPMfp4eK76qcJ9tLMThrQYc4Coz6BLmQoJKmX30K2/PNxOl1g KPz4mdXAKUn6PJ3SjPm5acpRuw3QgiOBjyWp1nBmsUBiShRq1PiEdGwW3FfM9PtsA8QP0MEH8gn FKppJ8TqHyJkTLGWNiw== X-Proofpoint-ORIG-GUID: 028Prj-d0QX_Ct5S-9hT16ZUKmVkrPTv X-Authority-Analysis: v=2.4 cv=X7rHu2Te c=1 sm=1 tr=0 ts=6aed433a cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=AEMvfOE69tE_Q1r2TxsA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDAxMSBTYWx0ZWRfX1hXF7E9qnuc1 pr3prw72UFvmDc1xvTVtQhA/pxIDIv7O4b9JF8r4En407QINZc3J3fghr7hus6HyKq3eODf4k7Y 5sOEpBMBGYhs+Yr/S+G9TIkg/B9ZFF4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_06,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060011 Expose SC7280's five CSIPHYs as standalone qcom,sc7280-csi2-phy generic-PHY provider nodes (csiphy0..4) at their existing register addresses, each with its own OF graph (port@0 sensor-facing, port@1 CAMSS-facing) so camss_detect_legacy_phy() picks the non-legacy path once a board wires a sensor through one of them. The camss node's own reg-names/clocks/interrupts for the CSIPHYs are unchanged, so boards that don't use a provider still get the legacy binding. csiphy_opp_table moves to the root node, not inside soc@0 (a simple-bus), since it has no reg/ranges property of its own. Its opp-300000000 and opp-400000000 entries are both kept unchanged: unlike SA8775P/QCS8300, SC7280's cam_cc_cphy_rx_clk_src defines both rates. The provider nodes are disabled by default; a board or camera overlay enables the one(s) it uses. Reviewed-by: Jigarkumar Zala Signed-off-by: Anusha Arun Nandi --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 172 +++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 8c7523602d27..e0e1fef7882e 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -968,6 +968,18 @@ opp-128000000 { }; }; + csiphy_opp_table: opp-table-csiphy { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -5164,6 +5176,166 @@ cci1_i2c1: i2c-bus@1 { }; }; + csiphy0: phy@ace0000 { + compatible = "qcom,sc7280-csi2-phy"; + reg = <0x0 0x0ace0000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + interrupts = ; + + operating-points-v2 = <&csiphy_opp_table>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + csiphy1: phy@ace2000 { + compatible = "qcom,sc7280-csi2-phy"; + reg = <0x0 0x0ace2000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + interrupts = ; + + operating-points-v2 = <&csiphy_opp_table>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + csiphy2: phy@ace4000 { + compatible = "qcom,sc7280-csi2-phy"; + reg = <0x0 0x0ace4000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + interrupts = ; + + operating-points-v2 = <&csiphy_opp_table>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + csiphy3: phy@ace6000 { + compatible = "qcom,sc7280-csi2-phy"; + reg = <0x0 0x0ace6000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + interrupts = ; + + operating-points-v2 = <&csiphy_opp_table>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + csiphy4: phy@ace8000 { + compatible = "qcom,sc7280-csi2-phy"; + reg = <0x0 0x0ace8000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + interrupts = ; + + operating-points-v2 = <&csiphy_opp_table>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + camss: isp@acb3000 { compatible = "qcom,sc7280-camss"; -- 2.34.1