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Thu, 5 Nov 2026 22:17:35 -0600 From: Sairaj Kodilkar To: "Joerg Roedel (AMD)" , Adrian Huang , Joerg Roedel , Robin Murphy , Suravee Suthikulpanit , Vasant Hegde , "Will Deacon" , , CC: Sairaj Kodilkar , Adam Pelka Subject: [PATCH v3 1/3] iommu/amd: Drop unused global exclusion range fields and init Date: Fri, 6 Nov 2026 09:46:48 +0530 Message-ID: <20261106041650.24076-2-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261106041650.24076-1-sarunkod@amd.com> References: <20261106041650.24076-1-sarunkod@amd.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|IA4PR12MB243497:EE_ X-MS-Office365-Filtering-Correlation-Id: 48eb184c-bf77-4fd5-62e8-08df3bbce52c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|82310400026|36860700016|261021121427099003|261022115727099003|261026130827099003|261026121527099003|11063799006|261026140227099003|56012099006|261021123027099003|261021130227099003|261021135927099003|261009223027099003|261022105027099003|261021133027099003|261022113327099003|261028144727099003|261026135527099003|261022075727099003|261102123227099003|10067099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hsXje55/nd4VnhhS2V0d6YIWVy1Dz8Rpn9hYF0ZwodlduRqxMm3VsGFwsWoolN6rFkYpSxthR0cEFGB3094f7HKQeWLsXcjsO8QHFvdsfYgKpTFK3LD4DAR3RUBgn6YsIoJnnxH8YISDLeoQquTyF/FQfOkuTLQAk8ccWG0ZfxijipgULOD46+avmIDx1yKR48XEc8Pc7JR/BLJrQhoOURECoMrBdrmBpcN8hjimz+M4SO0KdNXqjtWChZsMi/y5AwKvNBrvQmRt2+I/9qkMujZpD/27bmTKrrxhOiy5cEW8/EmZpqEf8/NW/NErXpTLbNwnXig4DdOkfNPcUAtyxUXIZDdfIrZgqxPSvuZkEzSLOs/foMH+n+7PrM/oChpv/PySe16Cl6QwSeX7NI6SuE22OAdSzvM7bkOZsro/16kpyvZQBBsI4vCli4echNwQ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 04:17:39.4129 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 48eb184c-bf77-4fd5-62e8-08df3bbce52c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA4PR12MB243497 From: Suravee Suthikulpanit Remove unused struct amd_iommu.exclusion_start/exclusion_length, the MMIO_EXCL_* flag masks, and iommu_set_exclusion_range(). These struct amd_iommu fields were never assigned, so early_enable_iommu() never programmed the hardware exclusion registers through this path. Please note that the exclusion range registers have been repurposed to SNP completion-wait store base / limit registers. So, rename MMIO_EXCL_BASE/LIMIT via to MMIO_COMPL_STORE_BASE/LIMIT instead. Signed-off-by: Suravee Suthikulpanit Signed-off-by: Sairaj Kodilkar Tested-by: Adam Pelka --- drivers/iommu/amd/amd_iommu_types.h | 4 ++-- drivers/iommu/amd/init.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 8241ef922519..678ceddd711c 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -44,8 +44,8 @@ #define MMIO_CMD_BUF_OFFSET 0x0008 #define MMIO_EVT_BUF_OFFSET 0x0010 #define MMIO_CONTROL_OFFSET 0x0018 -#define MMIO_EXCL_BASE_OFFSET 0x0020 -#define MMIO_EXCL_LIMIT_OFFSET 0x0028 +#define MMIO_COMPL_STORE_BASE_OFFSET 0x0020 +#define MMIO_COMPL_STORE_LIMIT_OFFSET 0x0028 #define MMIO_EXT_FEATURES 0x0030 #define MMIO_PPR_LOG_OFFSET 0x0038 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 8a410d4aa370..13c96feed64f 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -370,14 +370,14 @@ static void iommu_set_cwwb_range(struct amd_iommu *iommu) * Re-purpose Exclusion base/limit registers for Completion wait * write-back base/limit. */ - memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, + memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET, &entry, sizeof(entry)); /* Note: * Default to 4 Kbytes, which can be specified by setting base * address equal to the limit address. */ - memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, + memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_LIMIT_OFFSET, &entry, sizeof(entry)); } @@ -1022,7 +1022,7 @@ static int __init remap_or_alloc_cwwb_sem(struct amd_iommu *iommu) * completion wait buffer (CWB) address. Read and re-use it. */ pr_info_once("Re-using CWB buffers from the previous kernel\n"); - paddr = readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK; + paddr = readq(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET) & PM_ADDR_MASK; iommu->cmd_sem = iommu_memremap(paddr, PAGE_SIZE); if (!iommu->cmd_sem) return -ENOMEM; -- 2.34.1