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Thu, 05 Nov 2026 22:07:19 -0800 (PST) Received: from duge-G3-3500.taila331c7.ts.net ([183.192.220.13]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b25e4e079esm2780992c88.19.2026.11.05.22.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 22:07:19 -0800 (PST) From: Jiayu Du To: srini@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlan@kernel.org, troy.mitchell@linux.spacemit.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Jiayu Du Subject: [PATCH 3/3] riscv: dts: spacemit: Add K3 eFuse and temperature trim cells Date: Fri, 6 Nov 2026 14:05:25 +0800 Message-ID: <20261106060525.346873-4-duge1256@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261106060525.346873-1-duge1256@gmail.com> References: <20261106060525.346873-1-duge1256@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the K3 eFuse controller with its AES_WTM clock and reset. Describe fixed-layout cells for the temperature calibration parameters stored in bank 0 and bank 7, using controller-relative offsets. Leave the controller disabled for board-level enablement. Signed-off-by: Jiayu Du --- arch/riscv/boot/dts/spacemit/k3.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index e89d2cc5ca8c..51861fdc6a21 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -1439,6 +1439,31 @@ saplic: interrupt-controller@e0804000 { /* sec_i2c3: 0xf0614000, not available from Linux */ + efuse: efuse@f0702800 { + compatible = "spacemit,k3-efuse"; + reg = <0x0 0xf0702800 0x0 0x400>; + clocks = <&syscon_apmu CLK_APMU_AES_WTM>; + resets = <&syscon_apmu RESET_APMU_AES_WTM>; + + status = "disabled"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_rtemp_trim1: temperature-trim@120 { + reg = <0x120 0x1>; + bits = <0 8>; + }; + + soc_rtemp_trim: temperature-trim@19a { + reg = <0x19a 0x2>; + bits = <4 8>; + }; + }; + }; + mimsic: interrupt-controller@f1000000 { compatible = "spacemit,k3-imsics", "riscv,imsics"; reg = <0x0 0xf1000000 0x0 0x10000>; -- 2.43.0