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Thu, 05 Nov 2026 23:26:11 -0800 (PST) Received: from d.home.yangfl.dn42 ([2a09:bac1:7680:28::4:396]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ed47d89976sm2633715ad.66.2026.11.05.23.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 23:26:10 -0800 (PST) From: David Yang To: dmaengine@vger.kernel.org Cc: David Yang , Vinod Koul , Frank Li , Philipp Zabel , linux-kernel@vger.kernel.org Subject: [PATCH v2 0/2] dmaengine: pl08x: Support the Hi3798MV100 PL080 variant Date: Fri, 6 Nov 2026 15:25:57 +0800 Message-ID: <20261106072602.77560-1-mmyangfl@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi3798MV100 (HiSilicon HiSTB) carries a PL080-class DMAC. The block reports 0x0a141080 -- the ID reserved for Samsung's PL080S -- while its register map is plain PL080 and the instance has 4 channels instead of the 8 the plain PL080 entry claims. Set the DT node to arm,primecell-periphid = <0x00041080> and dma-channels = <4>, and apply the two patches to add that support. Tested on Hi3798MV100 hardware. v2: - fix for shared reset - use local copy of vendor_data v1: https://lore.kernel.org/r/20261104154542.3131916-1-mmyangfl@gmail.com/ David Yang (2): dmaengine: pl08x: Release the reset before reading registers dmaengine: pl08x: Use the channel count from the device tree drivers/dma/amba-pl08x.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) -- 2.53.0