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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: onwKKmKEEhFzeaxpZVi4ys5tX1T6dIyTSijSjyYScCak/YHuz7qFTU3ociNAVz2Nvabrn4a8zaT+hvzZ6TXNXIg0Nz7Mv5lnSPT1I1d6rq5CtXEkCt8cHFwFcxX9ljAkvZQAIWj5A1BUzuJ0Q+EBVPzns5538mEZhBvCBAuQUdZhnRNwSZQwhjEvF/uyF1IfNXGgPNHQMYOX5vp7Kps5L+yQ6vCXf7KMlIEF4P0o5e7nh5r6+y+uurDPgOW6DX/UCqiPScnIVBVKHdTonwjOVm8ey73AxPC4xECcgYx81F+tU+X//4f/6psIYhCXJXrwPvaPu/QQa2XmQCHX0pw0349SQPiX5Rx6tkWH4n0xJBmTFmBBhhZhUuFK5ppmDKRGRBcS8ikGKNG4q86gauCDVGo9wcF/sgUfy6pMGN+3Lh0T5M1dIOv8ooCzHVKOQcbE X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 10:12:12.5264 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6017d97-59bd-4b68-3541-08df3bee6d02 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66C9.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYPR06MB6062 This series adds support for the Cadence USBSSP DRD controller integrated in the CIX Sky1 SoC: the device tree binding and the glue driver. It is a USB series only. The arm64 device tree nodes belong to the SoC subsystem, so they are not part of this series and will be sent separately once the binding is accepted. Tested on Radxa Orion O6 (Sky1) in host mode, together with the CIX USB3 PHY series posted separately. The series applies on top of v7.4-rc1. Each controller is described as one address range in the USB30 Type-A DRD RCSU block at 0x091c0000, starting at its AXI cache attribute strap register and ending after its AXI clock status register. The two Type-A controllers interleave their strap and status registers in that block, so the two ranges overlap, and the range is mapped with devm_ioremap() instead of devm_platform_ioremap_resource(): requesting the region would make the second controller fail with -EBUSY. The register map of the block is in the binding commit message. Changes in v7: - Describe the RCSU registers of each controller as one address range starting at its AXI cache attribute register, instead of two 16-byte register slots, and drop the reg-names property. - Map that range with devm_ioremap(); request_mem_region() cannot be used because the two Type-A controllers share the block and their ranges overlap. - Take the offset of the AXI clock status register from per-compatible driver data (0xec on Type-A, 0xf0 on Type-C), instead of two reg-names. - Dropped #syscon-cells from the S5 system controller binding: the property does not exist in the kernel, and the series no longer touches bindings/soc/cix. - Removed the arm64 dts from the series: it is a separate SoC patchset. Changes in v6: - Dropped the simple-bus RCSU container; each node is placed at the address of its glue registers and the core is a child at its own address. - Replaced the usbN aliases and the undocumented id property with the register offset and bit position arguments of cix,usb-syscon. - Converted probe error paths to dev_err_probe(). - Removed the unused over-current GPIO handling and the unused dr_base and cdnsp_pdev fields. - Fixed the 125us prescaler value: time * frequency - 1. - Made the AXI halt writes read-modify-write so the preserved and RW1C bits of XEC_AXI_CAP keep their state. Changes in v5: - Dropped the cix,sky1-usbss-rcsu syscon binding and the cix,usb-rcsu phandle; the glue registers are described in the controller node. - Added the MAINTAINERS entry for the glue driver. Changes in v4: - Split the combined PHY/USBSSP series into two independent series. - Restructured the RCSU registers as a shared syscon region with offsets (reverted in v5). - Fixed the indentation reported by checkpatch. Changes in v3: - Fixed the interrupt specifiers of the core nodes: the Sky1 GICv3 uses four cells, so every entry needs the fourth (empty) cell. - PHY driver: assert the resets before registering the PHY provider, disable clocks in LIFO order, and fix the error unroll path so clocks that were never enabled are not disabled. Changes in v2: - Split the single binding into a PHY binding and a USBSSP binding. - clock-names: apb/ref for the PHY, sof/axi/lpm/apb for the controller. - reset-names: core/apb instead of reset/preset. - Dropped axi_bmax_value from DT; it is a driver constant. - Added the MAINTAINERS entries. Changes in v1: initial version. Hongliang Yang (2): dt-bindings: usb: Add CIX Sky1 USBSSP controller usb: cdns3: Add CIX Sky1 glue driver .../bindings/usb/cix,sky1-usbssp.yaml | 154 ++++ MAINTAINERS | 2 + drivers/usb/cdns3/Kconfig | 13 + drivers/usb/cdns3/Makefile | 1 + drivers/usb/cdns3/cdnsp-sky1.c | 710 ++++++++++++++++++ drivers/usb/cdns3/cdnsp-sky1.h | 100 +++ 6 files changed, 980 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml create mode 100644 drivers/usb/cdns3/cdnsp-sky1.c create mode 100644 drivers/usb/cdns3/cdnsp-sky1.h -- 2.54.0