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Each instance wraps one of the two USB3 Type-A DRD controllers of the SoC and owns a register range in the USB30 Type-A DRD RCSU block at 0x091c0000: offset register contents controller 0x0300 STRAP_PIN0 stream ID (SID/SSID) USB4 0x0304 STRAP_PIN1 stream ID (SID/SSID) USB5 0x030c STRAP_PIN3 clock enables, ctrl and PHYs USB4, USB5 0x0314 STRAP_PIN5 awcache[3:0], arcache[7:4] USB4 0x0324 STRAP_PIN9 awcache[3:0], arcache[7:4] USB5 0x0328 STRAP_PIN10 USB2 PLL controls USB4 0x0400 STRAP_STATUS0 AXI clock enable/valid/req USB4 0x0410 STRAP_STATUS4 AXI clock enable/valid/req USB5 Controller 0 of the block is used by USB4, controller 1 is used by USB5. The range of each instance starts at its own AXI cache attribute strap register and ends after its own AXI clock status register, so the two ranges overlap: the strap and status registers of the two controllers are interleaved in the block. The Cadence USBSSP core itself is described by a child node at its own address. Mode strap controls are programmed through the Sky1 S5 system controller referenced by the cix,usb-syscon phandle, whose arguments give the register offset and the bit position of the strap field. Signed-off-by: Hongliang Yang --- Changes in v7: - Describe the registers of each controller as one address range starting at its AXI cache attribute strap register, instead of two 16-byte register slots, and drop the reg-names property. - Document the register map of the shared RCSU block and the resulting overlap of the two ranges. - Do not touch the S5 system controller binding. Changes in v6: - Describe the glue registers at their real addresses instead of wrapping them in a simple-bus container with translated offsets. - Document the register offset and bit position arguments of the cix,usb-syscon phandle. - Document the ssp-disable and u3-port-disable properties read by the glue driver. - Fix the property order reported by sashiko. --- .../bindings/usb/cix,sky1-usbssp.yaml | 154 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml diff --git a/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml new file mode 100644 index 000000000000..137ef9ac1335 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cix,sky1-usbssp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 Cadence USBSSP Controller + +maintainers: + - Hongliang Yang + +description: | + The CIX Sky1 USBSSP controller is based on the Cadence USBSSP DRD + controller. Each instance wraps one of the two USB3 Type-A DRD + controllers of the SoC. + + The register range of an instance is a window in the USB30 Type-A DRD + RCSU block at 0x091c0000, starting at the AXI cache attribute strap + register of the instance and ending after its AXI clock status + register. The strap registers of the two controllers and of their PHYs + are interleaved in that block, so the ranges of the two instances + overlap. + + The Cadence USBSSP core itself is described by a child node at its own + address. Mode strap controls are programmed through the Sky1 S5 system + controller referenced by the cix,usb-syscon phandle, whose arguments + give the register offset and the bit position of the strap field. + +properties: + compatible: + const: cix,sky1-usbssp + + reg: + maxItems: 1 + description: + Window from the AXI cache attribute strap register of this instance + up to and including its AXI clock status register. + + ranges: true + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + clocks: + items: + - description: Start-of-frame clock + - description: AXI bus clock + - description: Low-power mode clock + - description: APB register interface clock + + clock-names: + items: + - const: sof + - const: axi + - const: lpm + - const: apb + + resets: + items: + - description: APB register reset + - description: Controller reset + + reset-names: + items: + - const: apb + - const: core + + ssp-disable: + type: boolean + description: Disable SuperSpeed Plus mode of the controller. + + u3-port-disable: + type: boolean + description: The board does not route the USB3 port of the controller. + + cix,usb-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle to the Sky1 S5 system controller followed by the register + offset and the bit position of the USB mode strap field. + items: + - items: + - description: Phandle to the Sky1 S5 system controller + - description: Register offset of the USB mode strap field + - description: Bit position of the USB mode strap field + +required: + - compatible + - reg + - ranges + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - resets + - reset-names + - cix,usb-syscon + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: cdns,usb3.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + usb@91c0314 { + compatible = "cix,sky1-usbssp"; + reg = <0x00 0x91c0314 0x00 0x100>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + clocks = <&scmi_clk CLK_TREE_USB3A_H0_CLK_SOF>, + <&scmi_clk CLK_TREE_USB3A_0_AXI_GATE>, + <&scmi_clk CLK_TREE_USB3A_H0_CLK_LPM>, + <&scmi_clk CLK_TREE_USB3A_0_APB_GATE>; + clock-names = "sof", "axi", "lpm", "apb"; + resets = <&src SKY1_USBC_SS2_PRST_N>, + <&src SKY1_USBC_SS2_RST_N>; + reset-names = "apb", "core"; + cix,usb-syscon = <&src 0x424 8>; + + usb@91d0000 { + compatible = "cdns,usb3"; + reg = <0x00 0x91d0000 0x00 0x4000>, + <0x00 0x91d8000 0x00 0x8000>, + <0x00 0x91d4000 0x00 0x4000>; + reg-names = "otg", "xhci", "dev"; + dr_mode = "otg"; + + interrupts = , + , + , + ; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + maximum-speed = "super-speed-plus"; + + phys = <&usb3_phy4_0>, <&usb2_phy6>; + phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy"; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 93abbb315065..5144d02fc998 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2903,6 +2903,7 @@ S: Maintained T: git https://github.com/cixtech/linux-mainline.git F: Documentation/devicetree/bindings/arm/cix.yaml F: Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml +F: Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml F: arch/arm64/boot/dts/cix/ F: drivers/mailbox/cix-mailbox.c K: \bcix\b -- 2.54.0