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Fri, 06 Nov 2026 02:13:09 -0800 (PST) Received: from dev.Default ([86.127.229.203]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-492d723310fsm2934846f8f.32.2026.11.06.02.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 02:13:09 -0800 (PST) From: Agustin Santiago Isasmendi To: Navid Ghahremani Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, stefandoesinger@gmail.com, krzk@kernel.org, Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v2 11/24] phy: zte: Add ZTE ZX279128S PCIe PHY driver Date: Fri, 6 Nov 2026 11:13:07 +0100 Message-Id: <20261106101307.3936492-2-isasmendi.agus@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20261014072109.1759502-12-ghahramani.navid@gmail.com> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> <20261014072109.1759502-12-ghahramani.navid@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Navid, On Wed, Oct 14, 2026 at 08:20:51AM +0100, Navid Ghahremani wrote: > + if (i == 0 && port->has_cal) { > + ret = regmap_write(zphy->regmap, CRM1_PHY1_CAL1, 0x00202d5a); > + if (ret) > + return ret; > + ret = regmap_write(zphy->regmap, CRM1_PHY1_CAL0, 0x0046c24a); On my unit both read back 0 after boot: there seems to be no register at 0x1b0/0x1b4 in the top CRM. The vendor kernel writes these two values into the port 1 controller's "ctrl" window instead (0x09600000 + 0x1b4, then + 0x1b0); with this series those read 0x00203c78 / 0x0c46c24a. The link trains anyway (the MT7916 enumerates at 2.5 GT/s), so it may only matter for signal margin, but as written the writes have no effect. Agustin