From: Christoph Hellwig <hch@lst.de>
To: Liao Xuan <liaoxuan@open-hieco.net>
Cc: kbusch@kernel.org, axboe@kernel.dk, hch@lst.de, sagi@grimberg.me,
linux-nvme@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] nvme-pci: Fix performance regression with completion batching for Hygon processors
Date: Fri, 6 Nov 2026 11:54:34 +0100 [thread overview]
Message-ID: <20261106105434.GB5905@lst.de> (raw)
In-Reply-To: <20261103063249.3212198-1-liaoxuan@open-hieco.net>
On Tue, Nov 03, 2026 at 02:32:49PM +0800, Liao Xuan wrote:
> Commit 4f5022453acd ("nvme: wire up completion batching for the IRQ path")
> introduced completion batching to the NVMe IRQ handling path. While this
> change brings performance gains on mainstream platforms, it causes a
> severe random read performance regression on Hygon platforms.
>
> The batching logic defers CQE processing until after the doorbell is
> written. On Hygon microarchitectures, this specific execution order
> accelerates the NVMe controller's interrupt generation. This leads to an
Why?
> Instead of hardcoding a permanent revert, introduce a flag 'use_comp_batch'
> and disable IRQ completion batching if running on a Hygon CPU. This
> preserves the performance benefits for platforms that favor batching
> while restoring the optimal single-completion fast path for Hygon, and
> provides a scalable mechanism to disable it on other affected platforms
> in the future.
No, these kinds of platform specific hacks do not belong into the
nvme driver.
prev parent reply other threads:[~2026-11-06 10:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 6:32 Liao Xuan
2026-11-06 10:54 ` Christoph Hellwig [this message]
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