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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from BL0PR12MB2370.namprd12.prod.outlook.com (2603:10b6:207:47::27) by IA1PR12MB6652.namprd12.prod.outlook.com (2603:10b6:208:38a::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.9; Fri, 6 Nov 2026 11:18:37 +0000 Received: from BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8]) by BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8%5]) with mapi id 15.21.0592.009; Fri, 6 Nov 2026 11:18:37 +0000 From: Richard Cheng To: bhelgaas@google.com, dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, benjamin.cheatham@amd.com Cc: iweiny@kernel.org, ming.li@zohomail.com, icheng@nvidia.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, tglx@kernel.org, wangruikang@iscas.ac.cn, vidyas@nvidia.com, lihaoxiang@isrc.iscas.ac.cn, xiangzao@linux.alibaba.com, shawn.lin@rock-chips.com, alifm@linux.ibm.com, 18255117159@163.com Subject: [PATCH v2 0/2] PCI/CXL: Guard MMIO accesses during reset recovery Date: Fri, 6 Nov 2026 19:18:27 +0800 Message-ID: <20261106111829.55823-1-icheng@nvidia.com> X-Mailer: git-send-email 2.50.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SI1PR02CA0023.apcprd02.prod.outlook.com (2603:1096:4:1f4::19) To BL0PR12MB2370.namprd12.prod.outlook.com (2603:10b6:207:47::27) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL0PR12MB2370:EE_|IA1PR12MB6652:EE_ X-MS-Office365-Filtering-Correlation-Id: f49df910-918c-4f0f-fe4e-08df3bf7b39a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|23010399003|366016|11063799006|56012099006|261009223027099003|261102123227099003|261026121527099003|261021121427099003|261028144727099003|261022075727099003|261022105027099003|261026140227099003|261021123027099003|10067099003|18002099003|6133799003; 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Accessing device MMIO in that state can cause additional errors, including DPC containment. This series adds checks before two MMIO access paths: MSI-X table resoration and CXL HDM decoder checking. Patch 1 checks the existing PCI Command register read in __pci_restore_msix_state(). If the read fails or returns all ones, warn and return before accessing the MSI-X table. Patch 2 guards CXL decoder accesses after reset. The CXL reset_done() callback independently accesses HDM decoder MMIO to check whether decoder state was lost during reset. Changes since v1 [1]: - Dropped v1 patch 1, since commit e8df1d194c39 ("PCI: Don't treat ~0 as ready in pci_dev_wait() with RRS SV") already addresses the issue. - Dropped v1 patch 2, following Benjamin Cheatham's review. That some devices rely on the existing fallback behavior. - Reworked v1 patch 3 into v2 patch 1. Instead of skipping all PCI state restoration, check config accessibility before MSI-X restoration. This reduces the impact on other restoration paths. - Retained v1 patch 4 as v2 patch 2. Richard Cheng (2): PCI/MSI: Skip MSI-X restoration when configuration is inaccessible cxl/pci: Guard decoder accesses after reset drivers/cxl/pci.c | 6 ++++++ drivers/pci/msi/msi.c | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-) base-commit: f66469d9905b39d2c260a15d7d6db450f4db67c1 -- 2.43.0