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[93.34.90.148]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4b76b5d52a7sm4849775e9.1.2026.11.06.03.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 03:59:05 -0800 (PST) From: Christian Marangi To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v11 4/5] clk: en7523: generalize register clocks function Date: Fri, 6 Nov 2026 12:58:49 +0100 Message-ID: <20261106115852.189098-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261106115852.189098-1-ansuelsmth@gmail.com> References: <20261106115852.189098-1-ansuelsmth@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Airoha AN7583 SoC will use the same logic used by Airoha EN7581 SoC to register clocks. Generalize it to register clocks defined in soc_data. Add the clocks definition in EN7581 SoC to support this new implementation. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index e534a5c91e61..8e24eef651a1 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -147,6 +147,7 @@ struct en_clk_priv { struct en_clk_soc_data { u32 num_clocks; + const struct en_clk_desc *base_clks; const struct clk_ops pcie_ops; int (*hw_init)(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data); @@ -818,12 +819,15 @@ static int en7523_clk_hw_init(struct platform_device *pdev, static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, struct regmap *map, void __iomem *base) { + const struct en_clk_soc_data *soc_data; struct clk_hw *hw; u32 rate; int i; - for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { - const struct en_clk_desc *desc = &en7581_base_clks[i]; + soc_data = device_get_match_data(dev); + + for (i = 0; i < soc_data->num_clocks - 1; i++) { + const struct en_clk_desc *desc = &soc_data->base_clks[i]; u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; int err; @@ -1308,6 +1312,7 @@ static const struct en_clk_soc_data en7523_data = { }; static const struct en_clk_soc_data en7581_data = { + .base_clks = en7581_base_clks, /* We increment num_clocks by 1 to account for additional PCIe clock */ .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1, .pcie_ops = { -- 2.55.0