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From: Fuad Tabba <fuad.tabba@linux.dev>
To: maz@kernel.org, tglx@kernel.org
Cc: radu@rendec.net, lpieralisi@kernel.org, steven.price@arm.com,
	suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, will@kernel.org, tabba@google.com
Subject: [PATCH 2/3] irqchip/gic-v3-its: Order table zeroing before the GIC can see it
Date: Fri,  6 Nov 2026 12:02:20 +0000	[thread overview]
Message-ID: <20261106120221.347309-3-fuad.tabba@linux.dev> (raw)
In-Reply-To: <20261106120221.347309-1-fuad.tabba@linux.dev>

The ITS driver allocates the GIC's tables as zeroed pages. It exposes
the ITS tables and the vPE tables with a single store: a relaxed
GITS_BASER or GICR_VPROPBASER write with Valid set, the relaxed
GITS_CTLR write that enables the ITS, or a valid level-1 entry for a
level-2 page. However, on a coherent table the zeroing isn't ordered
before that store, so the GIC can read the page's previous contents as
table entries (UNPREDICTABLE: IHI 0069H.b 5.2.1, and GICR_VPROPBASER.Z
in 12.11). A level-2 page is published at runtime, while the GIC may be
walking the same level-1 table for other IDs.

Add a dma_wmb() at the end of its_alloc_pages_node(). It orders the
zeroing before later stores to memory and to MMIO alike.

Signed-off-by: Fuad Tabba <fuad.tabba@linux.dev>
---

Notes:
    herd7 -model aarch64.cat, the ITS modelled as an observer PE that
    reads a published entry (e), then through it the zeroed page (p):
    with no barrier the stale read is Sometimes, with dma_wmb()'s
    DMB OSHST it is Never.
    
    AArch64 MP+dmb.st+addr-its-l1
    {
    0:X0=p; 0:X1=e; 0:X2=0; 0:X3=1;
    1:X1=e; 1:X0=p;
    p=1;
    }
     P0          | P1                ;
     STR X2,[X0] | LDR X4,[X1]       ;
     DMB OSHST   |                   ;
     STR X3,[X1] | EOR X5,X4,X4      ;
                 | LDR X6,[X0,X5]    ;
    exists (1:X4=1 /\ 1:X6=1)
    
    The model puts both PEs in one Inner Shareable domain, so it does
    not separate ISH from OSH. OSH reaches the GIC whichever domain it
    is in: DDI0487 B2.10.1.1 says Outer Shareable "applies across both
    the Inner Shareable and the Outer Shareable shareability domains".
    
    The register publishes (GITS_BASER, GITS_CTLR, GICR_VPROPBASER) are
    the writel() case: the same DMB OSHST ahead of a Device write.

 drivers/irqchip/irq-gic-v3-its.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index de1f1b1f26623..badc3843d90ca 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -234,6 +234,9 @@ static struct page *its_alloc_pages_node(int node, gfp_t gfp,
 	if (ret)
 		return NULL;
 
+	/* Order the zeroing before any store that exposes the page to the GIC */
+	dma_wmb();
+
 	return page;
 }
 
-- 
2.47.3


  parent reply	other threads:[~2026-11-06 12:02 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-06 12:02 [PATCH 0/3] irqchip/gic-v3-its: Fix how zeroed table pages reach the GIC Fuad Tabba
2026-11-06 12:02 ` [PATCH 1/3] irqchip/gic-v3-its: Zero ITS pages before sharing them with the host Fuad Tabba
2026-11-06 14:31   ` Suzuki K Poulose
2026-11-06 15:57     ` Fuad Tabba
2026-11-06 12:02 ` Fuad Tabba [this message]
2026-11-06 12:02 ` [PATCH 3/3] irqchip/gic-v3-its: Clean a non-shareable vPE table to PoC Fuad Tabba

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