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Fri, 6 Nov 2026 07:09:19 -0600 Received: from amd-System-Product-Name.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.53 via Frontend Transport; Fri, 6 Nov 2026 07:09:15 -0600 From: Vijendar Mukunda To: CC: , , , , , , , , , , , , , , , Subject: [PATCH 2/2] ASoC: amd: acp: document PDM controller topology for ACP7.B/7.F Date: Fri, 6 Nov 2026 18:37:29 +0530 Message-ID: <20261106130801.506026-3-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261106130801.506026-1-Vijendar.Mukunda@amd.com> References: <20261106130801.506026-1-Vijendar.Mukunda@amd.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PEPF000265B2:EE_|PH0PR12MB7789:EE_ X-MS-Office365-Filtering-Correlation-Id: 447c5988-cc4a-4554-d7b8-08df3c072bd0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|23010399003|18002099003|22082099003|10067099003|11063799006|261102123227099003|261021123027099003|261021121427099003|56012099006|261009223027099003; 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ASOC_SDW_ACP_DMIC (BIT(5)) is a generic DMIC-enable flag used across all ACP platforms; on ACP7.B/7.F it additionally identifies the PDM0 controller. ASOC_SDW_ACP_DMIC1 (BIT(6)) selects the PDM1 controller and is ACP7.B/7.F-specific. Both ACP7.B/7.F controllers support a 2-channel stereo capture path, and BIOS wires exactly one per platform. Signed-off-by: Vijendar Mukunda --- sound/soc/amd/acp/soc_amd_sdw_common.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/sound/soc/amd/acp/soc_amd_sdw_common.h b/sound/soc/amd/acp/soc_amd_sdw_common.h index 07837a2cfa54..21b059b74626 100644 --- a/sound/soc/amd/acp/soc_amd_sdw_common.h +++ b/sound/soc/amd/acp/soc_amd_sdw_common.h @@ -28,8 +28,15 @@ #define SOC_JACK_JDSRC(quirk) ((quirk) & GENMASK(3, 0)) #define ASOC_SDW_FOUR_SPK BIT(4) -#define ASOC_SDW_ACP_DMIC BIT(5) -#define ASOC_SDW_ACP_DMIC1 BIT(6) /* select DMIC1 controller for ACP7.B/7.F */ +/* + * ASOC_SDW_ACP_DMIC is a generic DMIC-enable flag used across all ACP + * platforms. On ACP7.B/7.F it additionally identifies the PDM0 controller; + * ASOC_SDW_ACP_DMIC1 selects PDM1 on ACP7.B/7.F instead. Both ACP7.B/7.F + * controllers support a 2-channel stereo capture path, and BIOS wires exactly + * one per platform. + */ +#define ASOC_SDW_ACP_DMIC BIT(5) /* enable DMIC; PDM0 on ACP7.B/7.F */ +#define ASOC_SDW_ACP_DMIC1 BIT(6) /* PDM1 / DMIC1, ACP7.B/7.F only */ #define ASOC_SDW_CODEC_SPKR BIT(15) #define AMD_SDW0 0 -- 2.53.0