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[24.20.225.94]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b0b323c18fsm8112112a91.4.2026.11.06.07.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 07:26:44 -0800 (PST) From: Nikolas Joshua Britton To: Ilpo =?utf-8?q?J=C3=A4rvinen?= Cc: Maciej Grochowski , Geramy Loveless , Eric Auger , Alexey Fomenko , Bjorn Helgaas , linux-pci@vger.kernel.org, Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?q?Wilczy=C5=84ski?= , Mesih Kilinc , linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 00/14] PCI: Resource placement algorithm fixes Date: Fri, 6 Nov 2026 15:26:42 +0000 Message-ID: <20261106152642.23118-1-nbritton@exabit.io> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261106134341.39493-1-ilpo.jarvinen@linux.intel.com> References: <20261106134341.39493-1-ilpo.jarvinen@linux.intel.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Fri, 6 Nov 2026, Ilpo Järvinen wrote: > There have been major changes so any retesting is appreciated (the > 4 candidates patch is largely the same so I kept the Tested-by tags but > everything around has been changing so even that is on the borderline > when it comes to the validity of the existing tags). I retested v5 on the Mac Pro 7,1 from my report (two Vega II Duo cards, four Vega 20 dies behind two root ports, BAR0 resized to 32G on every die). v7.3 and later don't boot on this machine for reasons unrelated to this series, so I tested on v7.2.15 plus 5012a6953208 ("PCI: Do not add hotplug reservation multiple times"), which 11/14 and 12/14 depend on. All 14 patches then apply as posted, and drivers/pci/setup-bus.c and drivers/pci/setup-res.c come out byte-identical to v7.4-rc1 + v5. Every BAR is assigned, both root port windows are 96G, and all four dies get their 32G BAR0. The first root port: pci 0000:06:00.0: bridge window [mem 0x9e800000000-0x9ffffffffff 64bit pref]: assigned pci 0000:07:00.0: bridge window [mem 0x9e800000000-0x9ffffffffff 64bit pref]: assigned pci 0000:08:08.0: bridge window [mem 0x9f7ffe00000-0x9ffffffffff 64bit pref]: assigned pci 0000:08:10.0: bridge window [mem 0x9e800000000-0x9f0001fffff 64bit pref]: assigned pci 0000:0b:00.0: BAR 0 [mem 0x9f800000000-0x9ffffffffff 64bit pref]: assigned pci 0000:0b:00.0: BAR 2 [mem 0x9f7ffe00000-0x9f7ffffffff 64bit pref]: assigned pci 0000:0e:00.0: BAR 0 [mem 0x9e800000000-0x9efffffffff 64bit pref]: assigned pci 0000:0e:00.0: BAR 2 [mem 0x9f000000000-0x9f0001fffff 64bit pref]: assigned The second root port (14:00.0) has the same layout at 0xbe800000000. Compared with v4, the two die chains swapped ends of the window: 08:08.0 and the windows nested below it (09:00.0, 0a:00.0) now sit at the top, with the 2M BAR2 at their left edge. That is the case the dropped nested-window fix covered, and it still assigns without that patch. amdgpu binds all four dies and compute across them works. Tested-by: Nikolas Joshua Britton