From: Chen Pei <cp0613@linux.alibaba.com>
To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org,
memxor@gmail.com, bjorn@kernel.org, puranjay@kernel.org,
alexei.starovoitov@gmail.com
Cc: eddyz87@gmail.com, martin.lau@linux.dev, song@kernel.org,
yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com,
ihor.solodrai@linux.dev, pulehui@huawei.com, pjw@kernel.org,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
luke.r.nels@gmail.com, xi.wang@gmail.com, shuah@kernel.org,
rgbi3307@gmail.com, guoren@kernel.org, bpf@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 bpf-next 0/3] riscv: bpf: Add BPF private stack support
Date: Sat, 7 Nov 2026 02:15:55 +0800 [thread overview]
Message-ID: <20261106181558.1564-1-cp0613@linux.alibaba.com> (raw)
This series adds private-stack support to the RV64 BPF JIT.
The verifier rejects a struct_ops program that requests a private stack
with -EACCES when the JIT does not report
bpf_jit_supports_private_stack(), and sched_ext requests one for its
dispatch callback, so no sched_ext scheduler can load on riscv64 today.
Allocation, the guard value and the lifetime handling follow arm64,
x86-64 and powerpc64; the 16 byte two-copy guard layout follows arm64
and powerpc64, since x86-64 uses an 8 byte guard with a single copy.
What is specific to riscv64 is where the pointers end up:
- Every BPF stack access goes through BPF_REG_FP (S5), so pointing S5
at the top of the per-CPU area and leaving SP on the kernel stack is
all the JIT has to do. S5 is callee-saved and each subprog derives
its own, so bpf2bpf calls need no extra save and restore.
- The outgoing stack argument area stays in the kernel frame: callers
write it relative to SP while callees read it relative to RV_REG_FP.
Unlike x86-64, no register here is shared with the private-stack
frame pointer, so no verifier-side exclusion is needed and stack
arguments keep working together with a private stack. arm64 already
does the same, and patch 3 tests that combination.
- The per-CPU lookup is emitted after the tail call entry point. A
program using a private stack can still be entered as a tail call
target, at RV_TAILCALL_OFFSET, so it has to set up its own S5 there;
and since that offset is a constant added to the target's bpf_func,
everything in front of it must be the same size in every program.
The base address is materialized with absolute moves, as on arm64,
x86-64 and powerpc64, which reach the per-CPU offset through gs:, TPIDR
or r13; riscv64 has no such register, so the address of __per_cpu_offset
is loaded too. Patch 1 has the detail, including why emit_imm() is a
choice there and why the prologue length stays fixed across passes.
RV32 does not declare support and keeps the existing behaviour; the
prologue signature is unchanged, so bpf_jit_comp32.c needs no edit.
Changes since v2:
- Patch 1: PRIV_STACK_GUARD_VAL moved to bpf_jit.h.
- Patch 3: The test redone as two asm programs in
progs/verifier_stack_arg.c.
Changes since v1:
- Patch 1 commit message: guard layout credited to arm64 and powerpc64,
value alone to x86-64; __per_cpu_offset described as a choice.
- Patch 3: test_private_stack_runtime() renamed to
serial_test_private_stack_runtime(), and the stack argument skip
prints a reason.
Testing
=======
QEMU virt rv64, an 8 vCPU SMP kernel and a 1 vCPU UP kernel, both built
on the base commit below, source tree clean at the head of this series,
selftests built from these patches. There are no private-stack related
failures, and the private-stack suites logged no BUG, WARNING, unknown
opcode or guard corruption. On UP, kfunc_call/subprog,
kfunc_call/subprog_lskel and scx_simple are not run: all three fail on
the unpatched base as well.
- verifier_private_stack, struct_ops_private_stack.
- tailcalls, stack_arg, subprogs, fentry_fexit, kfunc_call,
percpu_alloc, async_stack_depth, arena_atomics, arena_ldsx.
- verifier_stack_arg, stack_arg_precision.
- may_goto_priv_stack, may_goto_far, verifier_may_goto_1,
verifier_may_goto_2.
- scx_simple.
- sched_ext runner sweep on SMP: 40 cases, 39 pass. enable_cmask fails
because its ops.enable() takes a struct scx_cmask __arena pointer and
riscv64 does not implement bpf_jit_supports_arena_args().
- patch 3's test again on x86-64 and arm64, so all three
architectures it is gated on have run it.
Chen Pei (3):
riscv: bpf: Add BPF private stack support
selftests/bpf: Enable private stack tests for riscv64
selftests/bpf: Test a private stack together with stack arguments
arch/riscv/net/bpf_jit.h | 2 +
arch/riscv/net/bpf_jit_comp64.c | 42 +++++++++-
arch/riscv/net/bpf_jit_core.c | 82 +++++++++++++++++--
.../bpf/prog_tests/struct_ops_private_stack.c | 3 +-
.../bpf/progs/verifier_private_stack.c | 41 +++++++++-
.../selftests/bpf/progs/verifier_stack_arg.c | 49 +++++++++++
6 files changed, 205 insertions(+), 14 deletions(-)
base-commit: a3c8813409f13779fec225468aba7d4067a66468
--
2.50.1
next reply other threads:[~2026-11-06 18:16 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-06 18:15 Chen Pei [this message]
2026-11-06 18:15 ` [PATCH v3 bpf-next 1/3] " Chen Pei
2026-11-06 18:15 ` [PATCH v3 bpf-next 2/3] selftests/bpf: Enable private stack tests for riscv64 Chen Pei
2026-11-06 18:15 ` [PATCH v3 bpf-next 3/3] selftests/bpf: Test a private stack together with stack arguments Chen Pei
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