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Fri, 06 Nov 2026 14:16:10 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36faa5afffasm11333663eec.25.2026.11.06.14.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 14:16:09 -0800 (PST) From: Rosen Penev To: netdev@vger.kernel.org Cc: Chris Snook , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , Oleksij Rempel , linux-kernel@vger.kernel.org (open list) Subject: [PATCH net] net: ag71xx: let both QCA9550 MACs use MII, RGMII and SGMII Date: Fri, 6 Nov 2026 14:16:07 -0800 Message-ID: <20261106221607.16215-1-rosenp@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The GE0_SGMII bit of the QCA955x ETH_CFG register selects which GMAC gets the SerDes (QCA9558 datasheet, 10.8.1): when it is clear, GMAC0 connects as RGMII/MII and GMAC1 as SGMII, and when it is set, the other way around. The driver only allows the second layout, with SGMII on GMAC0 and RGMII/MII on GMAC1, but boards like the TP-Link Archer C7 use the first one, with GMAC0 on RGMII. Allow MII, RGMII and SGMII on both MACs. Tested on Archer C7 v2. RGMII on port 0 of the switch works. Fixes: 0767ec042897 ("net: ag71xx: extend link validation to support other SoCs") Signed-off-by: Rosen Penev --- drivers/net/ethernet/atheros/ag71xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c index 16434a7139bc..b2d78819a0a2 100644 --- a/drivers/net/ethernet/atheros/ag71xx.c +++ b/drivers/net/ethernet/atheros/ag71xx.c @@ -1079,7 +1079,7 @@ static int ag71xx_phylink_setup(struct ag71xx *ag) if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) || ag71xx_is(ag, AR9340) || ag71xx_is(ag, QCA9530) || - (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) + ag71xx_is(ag, QCA9550)) __set_bit(PHY_INTERFACE_MODE_MII, ag->phylink_config.supported_interfaces); @@ -1089,7 +1089,7 @@ static int ag71xx_phylink_setup(struct ag71xx *ag) __set_bit(PHY_INTERFACE_MODE_GMII, ag->phylink_config.supported_interfaces); - if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0) + if (ag71xx_is(ag, QCA9550)) __set_bit(PHY_INTERFACE_MODE_SGMII, ag->phylink_config.supported_interfaces); @@ -1098,7 +1098,7 @@ static int ag71xx_phylink_setup(struct ag71xx *ag) ag->phylink_config.supported_interfaces); if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) || - (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) + ag71xx_is(ag, QCA9550)) __set_bit(PHY_INTERFACE_MODE_RGMII, ag->phylink_config.supported_interfaces); -- 2.56.0