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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8b35921dc8bsm972135b3a.10.2026.11.06.15.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 15:23:25 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v7 14/15] drm/msm/a8xx: Switch to generated protect regs Date: Fri, 6 Nov 2026 15:21:06 -0800 Message-ID: <20261106232220.47602-15-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261106232220.47602-1-robin.clark@oss.qualcomm.com> References: <20261106232220.47602-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=A6j5rKWG c=1 sm=1 tr=0 ts=6aee616f cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=JcQOObtfp6PrThPhMQoA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDA5MyBTYWx0ZWRfX3q73T8vteZWi 3gQi6XYkBGloYTCJmnFQW6lRddL4r4+a7Isd293UeaM75g8VUSJm/A1ga+xzLSu6fMLX4KhgUdr bw50E12T3RvPUjf67wCI9EpSVM7sVOM5mPpo+sXyAEtvo85SlEo9xdlNBQQ5u/WK9wd0xbqC1Vj pls0LXcdDFGwEW1ug/TkRLVx0UFbrYCQccDppaq5RlG44sBCCOp2b5hVkBURBAvrPAqcB6LRy5d Sejvee7EiYWuRnjMbj66EyIZZsIc/0tKp4iADkMSX/JKxenaRPfXwJG+RfcfMnyDj/v+2RLQRlK tyt40K2+E3ljqDH6QmPmjBkatfupbnPlE+lI9ngXq8uijFK6PiFp6VKJwEAutuVW6YG8K0my9EF hPSmu1NxI2laXPe4TpZOXCZllH1G26PQJQ4yjXlEs4A2AVIWYRJUpCk7IxD7ClFjE/glSOWaTRL 6VOSIm82SZqFAY2QAxQ== X-Proofpoint-GUID: QJVymu30XtRmH0_hpiZrrIm05GEosP8N X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDA5MyBTYWx0ZWRfX5wcAp+xW8jK3 Bn//Al8tz5O1EnfO1Eepc9mQKQV3k29CVRkFERcovVkTQ6iUE/gXHYrq9MR4IPon8uIT+6Y4CHU V6d/Z2ROyuBmGjzzhsd0Z+uoAR8/bss= X-Proofpoint-ORIG-GUID: QJVymu30XtRmH0_hpiZrrIm05GEosP8N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-06_07,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 spamscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060093 These also fix some perfcntr SEL regs which were mistakenly blocked since we previously just copied the protect tables from downstream kgsl (and only sometimes remembered to fix these). Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_catalog.c | 301 +--------------------- 1 file changed, 13 insertions(+), 288 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c index 113a31158f8f..510c2f6017db 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c @@ -82,58 +82,6 @@ static const struct adreno_reglist_pipe a830_nonctxt_regs[] = { { }, }; -static const u32 a830_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x03a3), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0787), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x20000, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0381), - A6XX_PROTECT_NORDWR(0x27882, 0x0001), - A6XX_PROTECT_NORDWR(0x27c02, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a830_protect, 64); - static const u32 a830_pwrup_reglist_regs[] = { REG_A6XX_UCHE_MODE_CNTL, REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, @@ -364,63 +312,6 @@ static const struct adreno_reglist_pipe x285_nonctxt_regs[] = { { }, }; -static const u32 x285_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x0082c, 0x0000), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x000a), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; - -DECLARE_ADRENO_PROTECT(x285_protect, 15); - static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = { { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, @@ -522,57 +413,6 @@ static const struct adreno_reglist_pipe a810_nonctxt_regs[] = { { }, }; -static const u32 a810_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x03a3), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0787), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x20000, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0381), - A6XX_PROTECT_NORDWR(0x27882, 0x0001), - A6XX_PROTECT_NORDWR(0x27c02, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a810_protect, 64); - static const uint32_t a810_pwrup_reglist_regs[] = { REG_A6XX_UCHE_MODE_CNTL, REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, @@ -805,64 +645,6 @@ static const struct adreno_reglist_pipe a840_nonctxt_regs[] = { { }, }; -static const u32 a840_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x001b), - A6XX_PROTECT_NORDWR(0x00775, 0x000a), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_NORDWR(0x00c07, 0x0008), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x0009), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a840_protect, 15); - static const struct adreno_reglist a840_gbif[] = { { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 }, { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 }, @@ -1266,67 +1048,6 @@ static const struct adreno_reglist_pipe a850_nonctxt_regs[] = { { }, }; -static const u32 a850_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x001b), - A6XX_PROTECT_NORDWR(0x00775, 0x000a), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_NORDWR(0x00c07, 0x0008), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00df5, 0x0003), - A6XX_PROTECT_RDONLY(0x00df9, 0x0007), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1ac00, 0x1fff), - A6XX_PROTECT_NORDWR(0x1cc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x0035), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a850_protect, 15); - static const u32 a850_pwrup_reglist_regs[] = { REG_A8XX_RB_CMP_NC_MODE_CNTL, REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, @@ -1547,7 +1268,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a830_protect, + .protect = &pakala_protect, .nonctxt_reglist = a830_nonctxt_regs, .pwrup_reglist = &a830_pwrup_reglist, .dyn_pwrup_reglist = &a830_dyn_pwrup_reglist, @@ -1593,7 +1314,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_SOFTFUSE, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &x285_protect, + .protect = &glymur_protect, .nonctxt_reglist = x285_nonctxt_regs, .pwrup_reglist = &a840_pwrup_reglist, .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, @@ -1636,7 +1357,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a840_protect, + .protect = &kaanapali_protect, .nonctxt_reglist = a840_nonctxt_regs, .pwrup_reglist = &a840_pwrup_reglist, .dyn_pwrup_reglist = &a840_dyn_pwrup_reglist, @@ -1682,7 +1403,7 @@ static const struct adreno_info a8xx_gpus[] = { .funcs = &a8xx_gpu_funcs, .zapfw = "gen80300_zap.mbn", .a6xx = &(const struct a6xx_info) { - .protect = &a810_protect, + .protect = &milos_protect, .nonctxt_reglist = a810_nonctxt_regs, .pwrup_reglist = &a810_pwrup_reglist, .dyn_pwrup_reglist = &a810_dyn_pwrup_reglist, @@ -1725,7 +1446,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_SOFTFUSE, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &x285_protect, + .protect = &glymur_protect, .nonctxt_reglist = x285_nonctxt_regs, .pwrup_reglist = &a840_pwrup_reglist, .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, @@ -1768,7 +1489,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a850_protect, + .protect = &maili_protect, .nonctxt_reglist = a845_nonctxt_regs, .pwrup_reglist = &a850_pwrup_reglist, .dyn_pwrup_reglist = &a850_dyn_pwrup_reglist, @@ -1812,7 +1533,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a850_protect, + .protect = &hawi_protect, .nonctxt_reglist = a850_nonctxt_regs, .pwrup_reglist = &a850_pwrup_reglist, .dyn_pwrup_reglist = &a850_dyn_pwrup_reglist, @@ -1847,6 +1568,10 @@ DECLARE_ADRENO_GPULIST(a8xx); static inline __always_unused void __build_asserts(void) { - BUILD_BUG_ON(a810_protect.count > a810_protect.count_max); - BUILD_BUG_ON(a830_protect.count > a830_protect.count_max); + BUILD_BUG_ON(glymur_protect.count > glymur_protect.count_max); + BUILD_BUG_ON(hawi_protect.count > hawi_protect.count_max); + BUILD_BUG_ON(kaanapali_protect.count > kaanapali_protect.count_max); + BUILD_BUG_ON(maili_protect.count > maili_protect.count_max); + BUILD_BUG_ON(milos_protect.count > milos_protect.count_max); + BUILD_BUG_ON(pakala_protect.count > pakala_protect.count_max); } -- 2.56.0