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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b1057f0220sm658745a91.5.2026.11.06.15.22.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 15:22:36 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v7 01/15] drm/msm: Import adreno_snapshot.h Date: Fri, 6 Nov 2026 15:20:53 -0800 Message-ID: <20261106232220.47602-2-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261106232220.47602-1-robin.clark@oss.qualcomm.com> References: <20261106232220.47602-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: V-Jgz3WzisfgYq4DHL2aqelAOGGNb0cj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDA5MyBTYWx0ZWRfX12IFF2qtcERZ yip1T3nTqHQaxYr7LXQBZXMXi933xLLuArgICz5vyeYA1SwGNJ0puxnsEZBYBS3QUlqOA+IokqD Pps5GLuWWQ4hKCXcjmwoBGnq+gw7Zejv8dH3Db83P8UBpHxDOuU44VbHdSYv4/F4YkzOAPEKasC 5JSoKOwk6h0Xn00PAClhHCBq6cbk9Nf/3Rw0l/WYdee5lGnIli9LiRdahEhyD1MN9+cyXyBFAZ7 2hYUGBoBYtLytGoGL1Aj3qdHIR1wMN/k8eyyYLyAF6jd1JWoFh496gqRHSARG+qtGyrn/CTRWDY 9jnf1L1dA1durKZCA9oE5gbDMrwQRUoks9pJNoTareshjuyakv3PCGBwFIcW0psv5b+CPcskTMG ne2dLLM/e25oZSJUpb2lefuLtlnPo7dCAbMWbNphD4SEzeGCxi/1MXlWON5oxWVrDTwkSTVx+eN sOOoumi35aj/SQvLPCA== X-Authority-Analysis: v=2.4 cv=a6OlZkSF c=1 sm=1 tr=0 ts=6aee613e cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=brQcgiZQOO_HO4CFPnwA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDA5MyBTYWx0ZWRfX4a1QkZsDLAZg 0LJVHTpM0jQyuXxfbu2DrpwIMGaaTX2aHgz7Gp3Z2OetkiMCerLXtKJWquYdiHAOMcOfCCl7XPF INNJu+f71MPEZ+OM2QSpQ6HWAyJppws= X-Proofpoint-GUID: V-Jgz3WzisfgYq4DHL2aqelAOGGNb0cj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-06_07,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 phishscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 suspectscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060093 Based on kgsl_snapshot.h from downstream KMD. We'll be re-using some of this for gen8 devcoredump. Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_snapshot.h | 321 +++++++++++++++++++ 1 file changed, 321 insertions(+) create mode 100644 drivers/gpu/drm/msm/adreno/adreno_snapshot.h diff --git a/drivers/gpu/drm/msm/adreno/adreno_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_snapshot.h new file mode 100644 index 000000000000..f9956e0bc1d5 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/adreno_snapshot.h @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#pragma once + +#include + +/* Snapshot header */ + +/* High word is static, low word is snapshot version ID */ +#define SNAPSHOT_MAGIC 0x504D0002 + +#define DEBUG_SECTION_SZ(_dwords) (((_dwords) * sizeof(unsigned int)) \ + + sizeof(struct adreno_snapshot_debug)) + +/* GPU ID scheme: + * [16:31] - core identifer (0x0002 for 2D or 0x0003 for 3D) + * [00:16] - GPU specific identifier + */ + +struct adreno_snapshot_header { + __u32 magic; /* Magic identifier */ + __u32 gpuid; /* GPU ID - see above */ + /* Added in snapshot version 2 */ + __u32 chipid; /* Chip ID from the GPU */ +} __packed; + +/* Section header */ +#define SNAPSHOT_SECTION_MAGIC 0xABCD + +struct adreno_snapshot_section_header { + __u16 magic; /* Magic identifier */ + __u16 id; /* Type of section */ + __u32 size; /* Size of the section including this header */ +} __packed; + +/* Section identifiers */ +#define ADRENO_SNAPSHOT_SECTION_OS 0x0101 +#define ADRENO_SNAPSHOT_SECTION_REGS 0x0201 +#define ADRENO_SNAPSHOT_SECTION_REGS_V2 0x0202 +#define ADRENO_SNAPSHOT_SECTION_RB_V2 0x0302 +#define ADRENO_SNAPSHOT_SECTION_IB_V2 0x0402 +#define ADRENO_SNAPSHOT_SECTION_INDEXED_REGS 0x0501 +#define ADRENO_SNAPSHOT_SECTION_INDEXED_REGS_V2 0x0502 +#define ADRENO_SNAPSHOT_SECTION_DEBUG 0x0901 +#define ADRENO_SNAPSHOT_SECTION_DEBUGBUS 0x0A01 +#define ADRENO_SNAPSHOT_SECTION_GPU_OBJECT_V2 0x0B02 +#define ADRENO_SNAPSHOT_SECTION_MEMLIST_V2 0x0E02 +#define ADRENO_SNAPSHOT_SECTION_SHADER 0x1201 +#define ADRENO_SNAPSHOT_SECTION_SHADER_V2 0x1202 +#define ADRENO_SNAPSHOT_SECTION_SHADER_V3 0x1203 +#define ADRENO_SNAPSHOT_SECTION_MVC 0x1501 +#define ADRENO_SNAPSHOT_SECTION_MVC_V2 0x1502 +#define ADRENO_SNAPSHOT_SECTION_MVC_V3 0x1503 +#define ADRENO_SNAPSHOT_SECTION_GMU_MEMORY 0x1701 +#define ADRENO_SNAPSHOT_SECTION_SIDE_DEBUGBUS 0x1801 +#define ADRENO_SNAPSHOT_SECTION_TRACE_BUFFER 0x1901 +#define ADRENO_SNAPSHOT_SECTION_EVENTLOG 0x1A01 + +#define ADRENO_SNAPSHOT_SECTION_END 0xFFFF + +/* OS sub-section header */ +#define ADRENO_SNAPSHOT_OS_LINUX_V4 0x00000203 + +/* Linux OS specific information */ +struct adreno_snapshot_linux_v4 { + int osid; /* subsection OS identifier */ + __u32 seconds; /* Unix timestamp for the snapshot */ + __u32 power_flags; /* Current power flags */ + __u32 power_level; /* Current power level */ + __u32 power_interval_timeout; /* Power interval timeout */ + __u32 grpclk; /* Current GP clock value */ + __u32 busclk; /* Current busclk value */ + __u64 ptbase; /* Current ptbase */ + __u64 ptbase_lpac; /* Current LPAC ptbase */ + __u32 pid; /* PID of the process that owns the PT */ + __u32 pid_lpac; /* PID of the LPAC process that owns the PT */ + __u32 current_context; /* ID of the current context */ + __u32 current_context_lpac; /* ID of the current LPAC context */ + __u32 ctxtcount; /* Number of contexts appended to section */ + unsigned char release[32]; /* kernel release */ + unsigned char version[32]; /* kernel version */ + unsigned char comm[16]; /* Name of the process that owns the PT */ + unsigned char comm_lpac[16]; /* Name of the LPAC process that owns the PT */ +} __packed; + +/* + * This structure contains a record of an active context. + * These are appended one after another in the OS section below + * the header above + */ +struct adreno_snapshot_linux_context_v2 { + __u32 id; /* The context ID */ + __u32 timestamp_queued; /* The last queued timestamp */ + __u32 timestamp_consumed; /* The last timestamp consumed by HW */ + __u32 timestamp_retired; /* The last timestamp retired by HW */ +}; + +/* Ringbuffer sub-section header */ +struct adreno_snapshot_rb_v2 { + int start; /* dword at the start of the dump */ + int end; /* dword at the end of the dump */ + int rbsize; /* Size (in dwords) of the ringbuffer */ + int wptr; /* Current index of the CPU write pointer */ + int rptr; /* Current index of the GPU read pointer */ + int count; /* Number of dwords in the dump */ + __u32 timestamp_queued; /* The last queued timestamp */ + __u32 timestamp_retired; /* The last timestamp retired by HW */ + __u64 gpuaddr; /* The GPU address of the ringbuffer */ + __u32 id; /* Ringbuffer identifier */ +} __packed; + +/* Replay or Memory list section, both sections have same header */ +struct adreno_snapshot_mem_list_v2 { + /* + * Number of IBs to replay for replay section or + * number of memory list entries for mem list section + */ + int num_entries; + /* Pagetable base to which the replay IBs or memory entries belong */ + __u64 ptbase; +} __packed; + +/* Indirect buffer sub-section header (v2) */ +struct adreno_snapshot_ib_v2 { + __u64 gpuaddr; /* GPU address of the IB */ + __u64 ptbase; /* Base for the pagetable the GPU address is valid in */ + __u64 size; /* Size of the IB */ +} __packed; + +/* GMU memory ID's */ +#define SNAPSHOT_GMU_MEM_UNKNOWN 0x00 +#define SNAPSHOT_GMU_MEM_HFI 0x01 +#define SNAPSHOT_GMU_MEM_LOG 0x02 +#define SNAPSHOT_GMU_MEM_BWTABLE 0x03 +#define SNAPSHOT_GMU_MEM_DEBUG 0x04 +#define SNAPSHOT_GMU_MEM_BIN_BLOCK 0x05 +#define SNAPSHOT_GMU_MEM_CONTEXT_QUEUE 0x06 +#define SNAPSHOT_GMU_MEM_HW_FENCE 0x07 +#define SNAPSHOT_GMU_MEM_WARMBOOT 0x08 +#define SNAPSHOT_GMU_MEM_VRB 0x09 +#define SNAPSHOT_GMU_MEM_TRACE 0x0a + +/* GMU memory section data */ +struct adreno_snapshot_gmu_mem { + int type; + uint64_t hostaddr; + uint64_t gmuaddr; + uint64_t gpuaddr; +} __packed; + +/* Register sub-section header */ +struct adreno_snapshot_regs { + __u32 count; /* Number of register pairs in the section */ +} __packed; + +/* Indexed register sub-section header */ +struct adreno_snapshot_indexed_regs { + __u32 index_reg; /* Offset of the index register for this section */ + __u32 data_reg; /* Offset of the data register for this section */ + int start; /* Starting index */ + int count; /* Number of dwords in the data */ +} __packed; + +struct adreno_snapshot_indexed_regs_v2 { + u32 index_reg; /* Offset of the index register for this section */ + u32 data_reg; /* Offset of the data register for this section */ + u32 start; /* Starting index */ + u32 count; /* Number of dwords in the data */ + u32 pipe_id; /* Id of pipe, BV, Br etc */ + u32 slice_id; /* Slice ID to be dumped */ +} __packed; + +/* MVC register sub-section header */ +struct adreno_snapshot_mvc_regs { + int ctxt_id; + int cluster_id; +} __packed; + +struct adreno_snapshot_mvc_regs_v2 { + int ctxt_id; + int cluster_id; + int pipe_id; + int location_id; +} __packed; + +struct adreno_snapshot_mvc_regs_v3 { + u32 ctxt_id; + u32 cluster_id; + u32 pipe_id; + u32 location_id; + u32 slice_id; + u32 sp_id; + u32 usptp_id; +} __packed; + +/* Debug data sub-section header */ + +/* A5XX debug sections */ +#define SNAPSHOT_DEBUG_CP_MEQ 7 +#define SNAPSHOT_DEBUG_CP_PM4_RAM 8 +#define SNAPSHOT_DEBUG_CP_PFP_RAM 9 +#define SNAPSHOT_DEBUG_CP_ROQ 10 +#define SNAPSHOT_DEBUG_SHADER_MEMORY 11 +#define SNAPSHOT_DEBUG_CP_MERCIU 12 +#define SNAPSHOT_DEBUG_SQE_VERSION 14 + +/* GMU Version information */ +#define SNAPSHOT_DEBUG_GMU_CORE_VERSION 15 +#define SNAPSHOT_DEBUG_GMU_CORE_DEV_VERSION 16 +#define SNAPSHOT_DEBUG_GMU_PWR_VERSION 17 +#define SNAPSHOT_DEBUG_GMU_PWR_DEV_VERSION 18 +#define SNAPSHOT_DEBUG_GMU_HFI_VERSION 19 +#define SNAPSHOT_DEBUG_AQE_VERSION 20 + +/* Slice mask info */ +#define SNAPSHOT_DEBUG_SLICE_MASK 32 + +struct adreno_snapshot_debug { + int type; /* Type identifier for the attached tata */ + int size; /* Size of the section in dwords */ +} __packed; + +struct adreno_snapshot_debugbus { + int id; /* Debug bus ID */ + int count; /* Number of dwords in the dump */ +} __packed; + +struct adreno_snapshot_side_debugbus { + int id; /* Debug bus ID */ + int size; /* Number of dwords in the dump */ + int valid_data; /* Mask of valid bits of the side debugbus */ +} __packed; + +struct adreno_snapshot_shader { + int type; /* SP/TP statetype */ + int index; /* SP/TP index */ + int size; /* Number of dwords in the dump */ +} __packed; + +struct adreno_snapshot_shader_v2 { + int type; /* SP/TP statetype */ + int index; /* SP/TP index */ + int usptp; /* USPTP index */ + int pipe_id; /* Pipe id */ + int location; /* Location value */ + u32 size; /* Number of dwords in the dump */ +} __packed; + +struct adreno_snapshot_shader_v3 { + u32 type; /* SP/TP statetype */ + u32 slice_id; /* Slice ID */ + u32 sp_index; /* SP/TP index */ + u32 usptp; /* USPTP index */ + u32 pipe_id; /* Pipe id */ + u32 location; /* Location value */ + u32 ctxt_id; /* Context ID */ + u32 size; /* Number of dwords in the dump */ +} __packed; + +#define TRACE_BUF_NUM_SIG 4 + +/** + * enum trace_buffer_source - Bits to identify the source block of trace buffer information + * GX_DBGC : Signals captured from GX block + * CX_DBGC : Signals captured from CX block + */ +enum trace_buffer_source { + GX_DBGC = 1, + CX_DBGC = 2, +}; + +/** + * adreno_snapshot_trace_buffer: Header Information for the tracebuffer in snapshot. + */ +struct adreno_snapshot_trace_buffer { + /** @dbgc_ctrl: Identify source for trace */ + __u16 dbgc_ctrl; + /** @dbgc_ctrl: Identify source for trace */ + __u16 segment; + /** @granularity: The total number of segments in each packet */ + __u16 granularity; + /** @ping_blk: Signal block */ + __u16 ping_blk[TRACE_BUF_NUM_SIG]; + /** @ping_idx: Signal Index */ + __u16 ping_idx[TRACE_BUF_NUM_SIG]; + /** @size: Number of bytes in the dump */ + __u32 size; +} __packed; + +#define SNAPSHOT_GPU_OBJECT_SHADER 1 +#define SNAPSHOT_GPU_OBJECT_IB 2 +#define SNAPSHOT_GPU_OBJECT_GENERIC 3 +#define SNAPSHOT_GPU_OBJECT_DRAW 4 +#define SNAPSHOT_GPU_OBJECT_GLOBAL 5 + +struct adreno_snapshot_gpu_object_v2 { + int type; /* Type of GPU object */ + __u64 gpuaddr; /* GPU address of the object */ + __u64 ptbase; /* Base for the pagetable the GPU address is valid in */ + __u64 size; /* Size of the object (in dwords) */ +} __packed; + +struct adreno_snapshot_eventlog { + /** @type: Type of the event log buffer */ + __u16 type; + /** @version: Version of the event log buffer */ + __u16 version; + /** @size: Size of the eventlog buffer in bytes */ + u32 size; +} __packed; + +struct adreno_snapshot_gmu_version { + /** @type: Type of the GMU version buffer */ + u32 type; + /** @value: GMU FW version value */ + u32 value; +} __packed; + -- 2.56.0