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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b105831cf6sm653999a91.11.2026.11.06.15.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 15:22:40 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v7 03/15] drm/msm/a8xx: Add a8xx_aperture_acquire_raw() Date: Fri, 6 Nov 2026 15:20:55 -0800 Message-ID: <20261106232220.47602-4-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261106232220.47602-1-robin.clark@oss.qualcomm.com> References: <20261106232220.47602-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: qxarKYI4NMQoKH9tpxfDyMXs9hjX9B6h X-Authority-Analysis: v=2.4 cv=IdYSymqa c=1 sm=1 tr=0 ts=6aee6142 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=qGl0e74_xy6xiHm5yPkA:9 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDA5MyBTYWx0ZWRfX0bh5jSX9N0G9 Bu/MuzQvq9TtKoi8nJf8bxqqGKD4g3wWrWH/VLDbGHaP8wTiyuzgsAuXG/VBZMkEGhtfSf41ybw 0LNAFXmGtpVxi4GqYdMqaxUonUnHgok= X-Proofpoint-GUID: qxarKYI4NMQoKH9tpxfDyMXs9hjX9B6h X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDA5MyBTYWx0ZWRfX0x6AH1pQSB9Y rFmkC+AMj3FWAYaGphx/obLcWv1Up+PXlhmG5sMX4IqKVBEEv20LL9hlwhHYakO+lniwMKKt9AX DQ1e1fPTKx6dxfpCXUE6lkHUiJ11YBewvKHHbLGXMuDxtuH414N8XAcVOxnE+nIBgv/ko3puUwL cg/6QUTZWI4E0nWsXjUHSvo/TZXKQny+VojrvmLV6br+OXZYaMQILmbcw6MIO805gfBGLIrbBpr nK3mYubJZrbhjlTvzfCEpV0Pql8MhQt2roFDQHOxWtQCHaaX9ItWNaBfhOaJw+X4U+r/m46Jtg5 BtJkb9d4ZHUp0FhPXN/eOBOYiruagsgZnlRP2htaFXZm3KkZXKa6woaNK5iP8dhzCLv3qiNr5LR //G/XD+kk7XkHJDWzwvbqbYd1iEr47TJE0b4H8Xp5jPMSlMFb/UOr+EQmGUuX0lnOu92ml88krt 8Oaf/HSSOTUOCHwOojA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-06_07,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 phishscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060093 The snapshot code will need more control, setting additional bitfields. Rather than add a list of additional args, add a helper to acquire the aperture which directly takes a reg value. Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Reviewed-by: Akhil P Oommen Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 21 +++++++++++++-------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index c58a2665e9ab..e6ec85b20fb7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -346,6 +346,7 @@ void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); void a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring); int a6xx_zap_shader_init(struct msm_gpu *gpu); +void a8xx_aperture_acquire_raw(struct msm_gpu *gpu, u32 val, unsigned long *flags); void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags); void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags); void a8xx_aperture_clear(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 82cddaa7278f..be81f141300f 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -16,13 +16,10 @@ #define GPU_PAS_ID 13 -static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) +static void a8xx_aperture_slice_set(struct msm_gpu *gpu, u32 val) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - u32 val; - - val = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice); if (a6xx_gpu->cached_aperture == val) return; @@ -32,14 +29,20 @@ static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, a6xx_gpu->cached_aperture = val; } -void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +void a8xx_aperture_acquire_raw(struct msm_gpu *gpu, u32 val, unsigned long *flags) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); - a8xx_aperture_slice_set(gpu, pipe, 0); + a8xx_aperture_slice_set(gpu, val); + +} + +void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +{ + a8xx_aperture_acquire_raw(gpu, A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe), flags); } void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) @@ -74,8 +77,10 @@ static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 unsigned long flags; u32 val; - spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags); - a8xx_aperture_slice_set(gpu, pipe, slice); + a8xx_aperture_acquire_raw(gpu, + A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | + A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice), + &flags); val = gpu_read(gpu, offset); spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags); -- 2.56.0