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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cdb70a04a39sm1010142a12.15.2026.11.06.15.22.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 15:22:45 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Rob Clark , Konrad Dybcio , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v7 06/15] drm/msm/a8xx: Allow nonctx reglist to include GMU regs Date: Fri, 6 Nov 2026 15:20:58 -0800 Message-ID: <20261106232220.47602-7-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261106232220.47602-1-robin.clark@oss.qualcomm.com> References: <20261106232220.47602-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: aaVCS65NYOPkOgmMF3Xq1DNNV4V-hv2Q X-Authority-Analysis: v=2.4 cv=aNZlOr9m c=1 sm=1 tr=0 ts=6aee6147 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=cg0wMmP-TNBUvudz7-YA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDA5MyBTYWx0ZWRfX7D0oBldQMfOY wbXc9yY5HDEcm685LUN1KjqmLCqDLCUbhuvdBgYey6Tsbns7/6TXAuDBqumO16vtRZfhk6M2nMl HhJtDHEPZbKvRWaMGQ5gIQhUr5v2PEM= X-Proofpoint-GUID: aaVCS65NYOPkOgmMF3Xq1DNNV4V-hv2Q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDA5MyBTYWx0ZWRfX1AxTWf+Jg4QU 11zxzCmetkPMSdnIpdvD24/z0JLCjcPXCUFK/x4hbD3+8nQBWkxk9Y7mgjkMnwLq+CwGno8o0cf +YCPrGf8GhBWchOLsDW9JnSliy+xHUebZZGsmk5EmB0LZuZb2N0EfcnDjidiOQCcLQWJADVkpMi DzHcTVGyPkkMTm5Saya190Kd34RmYHvxQekQwOIoVikYfDM3w2HhC/E51g+TgIIHkq3+Y+h7WOi EvkN1BvhBwFJVW9qHOZTBaxYXKtNPS/49uYc6D85wXrbrtNnOc76P+7MtWWNc1H9mZn94yajqnX /r8z6yAF92jfHMHrvLZkkZeBEmD69gRPmI7MgST5SbKsJlPdFKcCjzn3FnXLz8WiwhI+oaGfroA RyyDMYm6ahaaA2+eE0VR1Na0Ln92RDyz/oJpmxy0+fEvK71dgjz1nE0q9wGm+31E4jb/e0jOpgn 3Y3YXJubEOM31Nerl4A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-06_07,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060093 >From hw PoV, it's all part of the GPU. But from dt perspective it is it's own device with a separate io space. So we need to detect this and direct writes to the correct place. Acked-by: Konrad Dybcio Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Reviewed-by: Akhil P Oommen Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index a29f8149493c..59898b49a201 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -373,6 +373,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; const struct a6xx_info *info = adreno_gpu->info->a6xx; const struct adreno_reglist_pipe *regs = info->nonctxt_reglist; unsigned int pipe_id, i; @@ -392,7 +393,11 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) *gmem_protect = regs[i].value; - gpu_write(gpu, regs[i].offset, regs[i].value); + if ((regs[i].offset << 2) >= gmu->mmio_offset) { + gmu_write(gmu, regs[i].offset, regs[i].value); + } else { + gpu_write(gpu, regs[i].offset, regs[i].value); + } } a8xx_aperture_release(gpu, flags); -- 2.56.0