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Do it so the caller does not need to program this register beforehand, which could leave the door open to bogus setups. Suggested-by: Eliot Courtney Link: https://lore.kernel.org/all/DMNWO08EFJD8.D2G9X082FUKN@nvidia.com/ Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index da860caac20b..76f49970cade 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -571,7 +571,7 @@ fn dma_wr( // // For untagged DMEM in a DMA object, the start offset is folded into the DMA base. For a // framebuffer address, the DMA engine adds the start offset to the address. - let (fb_offset, dma_base) = match src { + let (fb_offset, dma_base, fbif_target) = match src { FalconDmaSource::Sysmem(dma_obj) => { let (fb_offset, base_offset) = match target_mem { FalconMem::ImemSecure @@ -592,9 +592,12 @@ fn dma_wr( ( fb_offset, io_project!(dma_obj, [try: base_offset..dma_end]).dma_address(), + FalconFbifTarget::CoherentSysmem, ) } - FalconDmaSource::Framebuffer { base } => (load_offsets.src_start, base), + FalconDmaSource::Framebuffer { base } => { + (load_offsets.src_start, base, FalconFbifTarget::LocalFb) + } }; if dma_base % DmaAddress::from(DMA_LEN) > 0 { @@ -622,6 +625,12 @@ fn dma_wr( .with_size(DmaTrfCmdSize::Size256B) .with_falcon_mem(target_mem); + self.pfalcon + .update(regs::NV_PFALCON_FBIF_TRANSCFG::at(0), |v| { + v.with_target(fbif_target) + .with_mem_type(FalconFbifMemType::Physical) + }); + for pos in (0..num_transfers).map(|i| i * DMA_LEN) { // Perform a transfer of size `DMA_LEN`. self.pfalcon.write_reg( @@ -671,11 +680,6 @@ fn dma_load + FalconDmaLoadable>(&self, fw: &F) -> }; self.dma_reset(); - self.pfalcon - .update(regs::NV_PFALCON_FBIF_TRANSCFG::at(0), |v| { - v.with_target(FalconFbifTarget::CoherentSysmem) - .with_mem_type(FalconFbifMemType::Physical) - }); self.dma_wr( FalconDmaSource::Sysmem(&dma_obj), -- 2.56.0