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The r000 load-and-execute bootloader event can name any image for it to load, and the bootloader must then sit above the blocks that the image occupies, that is, in the last blocks of IMEM, regardless of its size. Place the bootloader at the top of the falcon's IMEM, using the IMEM size that the HWCFG register reports, instead of assuming a 64 KiB IMEM. Signed-off-by: John Hubbard Reviewed-by: Timur Tabi Reviewed-by: Zhi Wang [acourbot: split out of the patch separating the bootloader from FWSEC; convert the IMEM size with usize::from()] Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 7 +++++++ drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 7 ++++--- drivers/gpu/nova-core/firmware/gen_bootloader.rs | 21 +++++++++++++-------- drivers/gpu/nova-core/gsp/hal/tu102.rs | 6 ++++-- drivers/gpu/nova-core/regs.rs | 5 +++++ 5 files changed, 33 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index a34748abc74a..b17a997860ef 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -386,6 +386,13 @@ pub(crate) fn new( }) } + /// Returns the size of this falcon's IMEM in bytes. + pub(crate) fn imem_size(&self) -> usize { + let blocks = usize::from(self.pfalcon.read(regs::NV_PFALCON_FALCON_HWCFG).imem_size()); + + blocks * MEM_BLOCK_ALIGNMENT + } + /// Resets DMA-related registers. pub(crate) fn dma_reset(&self) { self.pfalcon.update(regs::NV_PFALCON_FBIF_CTL, |v| { diff --git a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs index 80239301bbfa..00f0d9704883 100644 --- a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs +++ b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs @@ -103,14 +103,15 @@ pub(crate) struct FwsecFirmwareWithBl<'a> { } impl<'a> FwsecFirmwareWithBl<'a> { - /// Loads the bootloader firmware for `dev` and `chipset`, and wrap `firmware` so it can be - /// loaded using it. + /// Loads the bootloader firmware for `dev` and `chipset`, placed at the top of `falcon`'s IMEM, + /// and wraps `firmware` so it can be loaded using it. pub(crate) fn new( firmware: FwsecFirmware, dev: &'a Device, chipset: Chipset, + falcon: &Falcon<'_, Gsp>, ) -> Result { - let bootloader = GenericBootloader::new(dev, chipset)?; + let bootloader = GenericBootloader::new(dev, chipset, falcon)?; // `BootloaderDmemDescV2` expects the source to be a mirror image of the destination and // uses the same offset parameter for both. diff --git a/drivers/gpu/nova-core/firmware/gen_bootloader.rs b/drivers/gpu/nova-core/firmware/gen_bootloader.rs index 16ef2c79a6b1..c4f436104326 100644 --- a/drivers/gpu/nova-core/firmware/gen_bootloader.rs +++ b/drivers/gpu/nova-core/firmware/gen_bootloader.rs @@ -12,13 +12,14 @@ TryIntoBounded, // }, prelude::*, - ptr::Alignable, - sizes, // + ptr::Alignable, // }; use crate::{ falcon::{ self, + gsp::Gsp, + Falcon, FalconPioImemLoadTarget, // }, firmware::tlv::{ @@ -40,15 +41,19 @@ pub(crate) struct GenericBootloader { } impl GenericBootloader { - /// Loads the generic bootloader image for `chipset`, placed right below the first 64 KiB of + /// Loads the generic bootloader image for `chipset`, placed in the last blocks of `falcon`'s /// IMEM. /// /// # Errors /// /// - `EINVAL` if a required TLV field is absent. - /// - `EOVERFLOW` if the image does not fit below 64 KiB. + /// - `EOVERFLOW` if the image does not fit in IMEM. /// - `ENOMEM` if the padded copy of the code cannot be allocated. - pub(crate) fn new(dev: &device::Device, chipset: Chipset) -> Result { + pub(crate) fn new( + dev: &device::Device, + chipset: Chipset, + falcon: &Falcon<'_, Gsp>, + ) -> Result { let fw = request_tlv(dev, chipset, "gen_bootloader")?; let tlv = Tlv::new(fw.data())?; dev_dbg!( @@ -72,9 +77,9 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset) -> Result { ucode }; - // The bootloader's code must be loaded in the area right below the first 64K of IMEM. - const BOOTLOADER_LOAD_CEILING: usize = sizes::SZ_64K; - let imem_dst_start = BOOTLOADER_LOAD_CEILING + // The top of IMEM, above the blocks that the bootloader loads the image into. + let imem_dst_start = falcon + .imem_size() .checked_sub(ucode.len()) .ok_or(EOVERFLOW)?; diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core/gsp/hal/tu102.rs index e90db1a23032..1b17ece53bd6 100644 --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -165,7 +165,7 @@ fn run_fwsec_frts( )?; if self.needs_fwsec_bootloader { - let fwsec_frts_bl = FwsecFirmwareWithBl::new(fwsec_frts, dev, chipset)?; + let fwsec_frts_bl = FwsecFirmwareWithBl::new(fwsec_frts, dev, chipset, falcon)?; // Load and run the bootloader, which will load FWSEC-FRTS and run it. fwsec_frts_bl.run(dev, falcon)?; } else { @@ -223,7 +223,9 @@ fn build_unload_bundle<'gpu>( // Load the FWSEC SB firmware, as well as its bootloader if required. let fwsec_sb = FwsecFirmware::new(dev, gsp_falcon, bios, FwsecCommand::Sb)?; let fwsec_sb = if self.needs_fwsec_bootloader { - FwsecUnloadFirmware::WithBl(FwsecFirmwareWithBl::new(fwsec_sb, dev, chipset)?) + FwsecUnloadFirmware::WithBl(FwsecFirmwareWithBl::new( + fwsec_sb, dev, chipset, gsp_falcon, + )?) } else { FwsecUnloadFirmware::WithoutBl(fwsec_sb) }; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index bf3a43f1c09e..af0bbb92e992 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -181,6 +181,11 @@ pub(crate) fn usable_fb_size(self) -> u64 { 31:0 value => u32; } + pub(crate) NV_PFALCON_FALCON_HWCFG(u32) @ 0x00000108 { + /// Number of 256-byte blocks in this falcon's IMEM. + 8:0 imem_size; + } + pub(crate) NV_PFALCON_FALCON_DMACTL(u32) @ 0x0000010c { 7:7 secure_stat => bool; 6:3 dmaq_num; -- 2.56.0