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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36faac86a96sm11069040eec.29.2026.11.06.18.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 18:39:30 -0800 (PST) From: Himanshu Chauhan To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Cc: Alexandre Ghiti , Jesse Taube , Oleg Nesterov , Kees Cook , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Shuah Khan , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Himanshu Chauhan Subject: [PATCH v8 0/8] riscv: Introduce support for hardware break/watchpoints Date: Sat, 7 Nov 2026 08:09:09 +0530 Message-ID: <20261107023917.40606-1-himanshu.chauhan@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA3MDAxMCBTYWx0ZWRfX6FAySnO6mWiO LqPqyvgMniBnMw5PNgIDsmPRMpnQl+OJFuAKvym+iyP+o50e4wdYBY++DDO7W+xMXU2tlAtALOj sNHhHS5bOlNW8D8pNT3owDKH1U9mqKymAZ6wpPCumJC/N/T7roQDkq7dJbVXD/FEQWnf007AyL8 FTc8nfT16fUnJFUJmzDJ+ngaop2RJmr4dlXgfRtojsuZrorUfQDrZsyXiuiTOtpyA4mnKEG8Zmv l5ssXAOj5OfCWowyHHhbZ8NVSeo35nvx9+zyFAkhHA3Ii0mtdoo4gkmV76F4OusnQ5f3Pe8INxg KBC/QZc4+PifP4baErJCt+LJLOb15CBMbHdCTSazOiG2nk3DonyMMm0oqw7DtT2haH+HA3q1rvg JOolsvsF2vErdmTaM40hS9B51LBXdje17IelntrNLBhjgZSBis+kxIi/GQuMUAVUSigsRLxPpjF 6WZioeXBJ2NN52hxyXQ== X-Proofpoint-GUID: qXw5EuG57R5ogsuAtKegpjS-asCsU-NJ X-Authority-Analysis: v=2.4 cv=IJGXmQvG c=1 sm=1 tr=0 ts=6aee8f65 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=NEAV23lmAAAA:8 a=HwFc7jivAAAA:8 a=_NFv3PjsgsRmLWfyS6wA:9 a=PxkB5W3o20Ba91AHUih5:22 a=kr7TZk85JJIQSqC0cl8G:22 X-Proofpoint-ORIG-GUID: qXw5EuG57R5ogsuAtKegpjS-asCsU-NJ X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA3MDAxMCBTYWx0ZWRfXzsLH6CvvsJVe AGU5OxyvPHkUFLR1eVkPR+lWl8x5JLFn3v8eICEm+kDGZqpJ9kHOr/iS33KbiSfxiVy8Pm5YYt+ XFhaa+ieBWrlZdRId3swO7ZWc4BPoUk= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-07_01,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 impostorscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611070010 This patchset adds support for hardware breakpoints and watchpoints in the RISC-V architecture. The framework is built on top of the perf/ptrace subsystem and the SBI debug trigger extension (Sdtrig). Single stepping uses icount when it is available. The software stepping path is kept as a fallback for systems where icount is not available. The icount path depends on a QEMU fix so that, when an icount trigger fires, the exception PC follows the Sdtrig action rule: "xepc must contain the virtual address of the next instruction that must be executed to preserve the program flow." For QEMU testing, please use: https://github.com/hschauhan/qemu/tree/hschauhan/sdtrig-icount-fix Virtualization of debug triggers is pending. The patch set is ready but needs testing. Changes from v7: - Rebased to v7.4-rc1 and folded maintainer entries into the patches that add the maintained files. - Reworked the patch structure: - one patch for the direct single-slot ptrace requests - one patch for the register set interface - debug trigger encoding details kept internal from the introductory patch - Tightened breakpoint and watchpoint handling: - trigger setup, update, uninstall, cleanup, and error paths - debug trap races with trigger programming - hit state cleanup so stale hardware state is not reused - cleanup across program replacement and fork - bounds, overflow, and wider-access watchpoint matching - Improved ptrace support: - both ptrace interfaces now share the same breakpoint/watchpoint storage - 32-bit traced tasks are supported on 64-bit kernels - partial writes and bad indexes are rejected more carefully - Improved single stepping: - icount is used when available, so the hardware reports the next PC and the kernel does not have to decode the stepped instruction - software stepping remains as the fallback and now handles indirect branches, kernel-address instruction fetches, and mode-specific temporary triggers more carefully - unsafe software-step cases are rejected instead of looping on the same address, and the original breakpoint is restored if stepping lands somewhere unexpected - CPU-wide software stepping is rejected when icount is unavailable; there is no task to follow, and the fallback needs per-task state - unused saved trigger state was removed, and the QEMU icount fix needed for testing is documented - Improved selftests: - icount stepping over a taken branch - cleanup of failed child processes - failure propagation to the process exit status - bounded waits for expected signals - breakpoint/watchpoint readback validation - native riscv64 build handling and RISC-V-only test flags - Built and tested QEMU, OpenSBI, Linux, the breakpoint selftest, perf tests, RV32 compat ptrace tests, icount stepping, and software-step fallback Changes from v6: - Rebased to v7.3-rc5 - Added HIT0/1 bit check/clear in breakpoint handler with EPC/Bp address check - Removed dbtr_shmem null check as pointed by Qinfang Deng - Fixed MEM_HI/MEM_LO macros to work both on rv64/32 - Changed unsigned long to __u64 from hwdebug state struct and dropped packing - Gated HAVE_MIXED_BREAKPOINT_REGS with PERF_EVENTS - Software base single stepping with mcontrol6 trigger type. - icount is still under development. - Moved and and reworked instruction decoding code to a common file. - perf test suite now supported. - Breakpoint overflow signal handler - Breakpoint overflow sampling - Breakpoint accounting (needs sudo) - Watchpoint - Read Only Watchpoint - Write Only Watchpoint - Read / Write Watchpoint - Modify Watchpoint - __test_function in "Breakpoint overflow signal handler" is name noinline - Fixed warnings from checkpatch.pl --strict Changes from v5: - Rebased to v7.2-rc6 - Simplified Macros in hw_breakpoint.h - Took care of the review comments - Added ptrace support for hardware break/watchpoints (new patch) - PTRACE_GETREGSET/SETREGSET via NT_RISCV_HW_BREAK / NT_RISCV_HW_WATCH - PTRACE_GETHBPREGS / SETHBPREGS for direct single-trigger access - HAVE_MIXED_BREAKPOINTS_REGS selected (break/watch share trigger pool) - flush_ptrace_hw_breakpoint / ptrace_hw_copy_thread wired up - Extended selftest to cover ptrace-based hw break/watchpoint paths (new patch) Changes from v4: - Rebased to v7.2-rc4 - Fixed rv32 build error - Added pr_fmt to print KBUILD_MODNAME - Changed type of shmem_pa to phys_addr_t - Use per_cpu_ptr_to_phys instead of __pa for per-cpu allocated memory - Print successful registration/unregistration message when no error - Added RISC-V DEBUGGING section in MAINTAINERS and added myself as maintainer - Fixed warnings from checkpatch.pl --strict run Changes from v3: - Rebased to v7.1-rc3 - For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and keep STVAL-based matching as fallback - Improved watchpoint matching when STVAL reports the lowest accessed address for wider memory accesses - Program execute breakpoints with SIZE=0 (match any size) to avoid misses with 16-bit/compressed instruction addresses - Updated selftest to avoid deadlock by replacing unbounded sem_wait() with sem_timedwait() timeout handling - Updated selftest breakpoint function so it cannot be inlined or optimized away Changes from v2: - Rebased to v7.0-rc1 - Fixed warnings from checkpatch.pl --strict run Changes from v1: - The patch adding the SBI extension and function IDs is already merged; this series builds on top of that - Added breakpoint selftest in tools/testing/selftests/breakpoints/ Specifications: ~~~~~~~~~~~~~~ The SBI debug trigger extension is specified in the SBI specification: https://docs.riscv.org/reference/sbi/v3.0/ext-debug-triggers.html The Sdtrig ISA is part of the RISC-V debug specification: https://github.com/riscv/riscv-debug-spec How to use: ~~~~~~~~~~~ OpenSBI: https://github.com/riscv-software-src/opensbi.git QEMU: https://github.com/hschauhan/qemu/tree/hschauhan/sdtrig-icount-fix Linux Kernel: Apply these patches on top of v7.4-rc1 How to test: ~~~~~~~~~~~ >>From the Linux kernel directory, first install the UAPI headers (required on a fresh tree so the compiler can locate and the new NT_RISCV_HW_BREAK/WATCH definitions via KHDR_INCLUDES): make headers Then build the selftest: make -C tools/testing/selftests/breakpoints/ This produces breakpoint_test_riscv under the same directory. Load it on the target and run. Sample output: # /apps/breakpoint_test_riscv # [perf_event]: Breakpoint test passed! # [perf_event]: Watchpoint test passed! # [ptrace]: Breakpoint test passed! # ptrace(PTRACE_GETREGSET): Number of watchpoints: 2 # ptrace(PTRACE_GETREGSET): addr: 0x82888 control: 0x8080 # [ptrace]: Watchpoint test passed! # [hbpregs] breakpoint readback: addr=0x10472 type=4 len=4 ctrl=0 # [hbpregs]: Breakpoint test passed! # [hbpregs] watchpoint readback: addr=0x82888 type=2 len=8 ctrl=0 # [hbpregs]: Watchpoint test passed! # Icount taken branch PC test passed! Perf Test Suite: ~~~~~~~~~~~~~~~ Run these perf tests sequentially. On this perf tree, the watchpoint tests share one watched variable and the default parallel mode can make the subtests interfere with each other. ~ # /apps/perf test -S -v 16 17 18 19 20 16: Breakpoint overflow signal handler : Ok 17: Breakpoint overflow sampling : Ok 18: Event re-armed with PERF_EVENT_IOC_REFRESH : 18.1: Software event : Ok 18.2: Tracepoint event : Skip (permissions) 19: Breakpoint accounting : Ok 20: Watchpoint : 20.1: Read Only Watchpoint : Ok 20.2: Write Only Watchpoint : Ok 20.3: Read / Write Watchpoint : Ok 20.4: Modify Watchpoint : Ok === Test Summary === Passed main tests : 3 Passed subtests : 5 Skipped tests : 1 Failed tests : 0 Himanshu Chauhan (8): riscv: Introduce support for hardware break/watchpoints riscv: Add breakpoint and watchpoint test for riscv riscv: add ptrace requests for hardware breakpoints riscv: add regset access for hardware breakpoints selftests/breakpoints: extend riscv test for ptrace hw break/watchpoints riscv: Add shared instruction fetch and decode helpers riscv: Add software supported single stepping with mc/mc6 triggers perf tests: keep bp_signal memory accesses visible MAINTAINERS | 12 + arch/riscv/Kconfig | 2 + arch/riscv/include/asm/hw_breakpoint.h | 78 ++ arch/riscv/include/asm/insn.h | 16 + arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/include/asm/processor.h | 15 + arch/riscv/include/uapi/asm/ptrace.h | 50 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/hw_breakpoint.c | 1182 +++++++++++++++++ arch/riscv/kernel/process.c | 2 + arch/riscv/kernel/ptrace.c | 661 +++++++++ arch/riscv/kernel/traps.c | 6 + arch/riscv/kernel/traps_misaligned.c | 52 +- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/insn.c | 279 ++++ include/uapi/linux/elf.h | 4 + tools/include/uapi/linux/elf.h | 2 + tools/perf/tests/bp_signal.c | 14 +- tools/testing/selftests/breakpoints/Makefile | 8 + .../breakpoints/breakpoint_test_riscv.c | 867 ++++++++++++ 20 files changed, 3197 insertions(+), 58 deletions(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c create mode 100644 arch/riscv/lib/insn.c create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c -- 2.43.0