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Sat, 07 Nov 2026 05:21:06 -0800 (PST) Received: from d.home.yangfl.dn42 ([2a09:bac1:76a0:28::1d2:30]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b101d3d0e8sm1626521a91.3.2026.11.07.05.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Nov 2026 05:21:06 -0800 (PST) From: David Yang To: netdev@vger.kernel.org Cc: David Yang , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/4] net: dsa: motorcomm: Use safe 64-bit counter reader Date: Sat, 7 Nov 2026 21:20:35 +0800 Message-ID: <20261107132040.1066996-4-mmyangfl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261107132040.1066996-1-mmyangfl@gmail.com> References: <20261107132040.1066996-1-mmyangfl@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 64-bit counter registers are read as two separate 32-bit transactions. If the low word wraps from about 0xffffffff to a small value while the high word increments between the two transactions, the recombined value becomes ((new_high << 32) | old_low), producing a spurious ~4 GiB jump. Use a safe counter reader for this. Signed-off-by: David Yang Reviewed-by: Andrew Lunn --- drivers/net/dsa/motorcomm/mib.c | 21 +++++++++----------- drivers/net/dsa/motorcomm/smi.c | 35 +++++++++++++++++++++++++++++++++ drivers/net/dsa/motorcomm/smi.h | 2 ++ 3 files changed, 46 insertions(+), 12 deletions(-) diff --git a/drivers/net/dsa/motorcomm/mib.c b/drivers/net/dsa/motorcomm/mib.c index 90b0ef670aa3..b45bc8211741 100644 --- a/drivers/net/dsa/motorcomm/mib.c +++ b/drivers/net/dsa/motorcomm/mib.c @@ -102,29 +102,26 @@ static int yt921x_mib_read(struct yt921x_priv *priv, int port) for (size_t i = 0; i < ARRAY_SIZE(yt921x_mib_descs); i++) { const struct yt921x_mib_desc *desc = &yt921x_mib_descs[i]; u32 reg = YT921X_MIBn_DATA0(port) + desc->offset; - u32 val0; - u64 val; - - res = yt921x_reg_read(priv, reg, &val0); - if (res) - break; if (desc->size <= 1) { u64 old_val = buf[i]; + u32 val0; + u64 val; + + res = yt921x_reg_read(priv, reg, &val0); + if (res) + break; val = (old_val & ~(u64)U32_MAX) | val0; if (val < old_val) val += 1ull << 32; - } else { - u32 val1; - res = yt921x_reg_read(priv, reg + 4, &val1); + buf[i] = val; + } else { + res = yt921x_counter_read(priv, reg, &buf[i]); if (res) break; - val = ((u64)val1 << 32) | val0; } - - buf[i] = val; } flags = u64_stats_update_begin_irqsave(&pm->syncp); diff --git a/drivers/net/dsa/motorcomm/smi.c b/drivers/net/dsa/motorcomm/smi.c index bf3adfd64165..16f62409422d 100644 --- a/drivers/net/dsa/motorcomm/smi.c +++ b/drivers/net/dsa/motorcomm/smi.c @@ -63,6 +63,41 @@ int yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, u32 val) return yt921x_reg_write(priv, reg, u); } +/* Reliably read a 64-bit counter, assuming the counter isn't that "fast" */ +int yt921x_counter_read(struct yt921x_priv *priv, u32 reg, u64 *valp) +{ + u32 old_lo; + int res; + u32 hi; + u32 lo; + + res = yt921x_reg_read(priv, reg, &old_lo); + if (res) + return res; + + res = yt921x_reg_read(priv, reg + 4, &hi); + if (res) + return res; + + res = yt921x_reg_read(priv, reg, &lo); + if (res) + return res; + + if (lo < old_lo) { + u32 new_hi; + + res = yt921x_reg_read(priv, reg + 4, &new_hi); + if (res) + return res; + if (new_hi != hi + 1) + return -EIO; + hi = new_hi; + } + + *valp = ((u64)hi << 32) | lo; + return 0; +} + static int yt921x_regs_read(struct yt921x_priv *priv, u32 reg, u32 *vals, unsigned int num_regs) diff --git a/drivers/net/dsa/motorcomm/smi.h b/drivers/net/dsa/motorcomm/smi.h index 212e20f71d80..d34240548af7 100644 --- a/drivers/net/dsa/motorcomm/smi.h +++ b/drivers/net/dsa/motorcomm/smi.h @@ -35,6 +35,8 @@ yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32 reg, u32 mask, bool set) return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); } +int yt921x_counter_read(struct yt921x_priv *priv, u32 reg, u64 *valp); + /* Some multi-word registers, like VLANn_CTRL, should be treated as a single * long register. More specifically, writes to parts of its words won't become * visible, until the last word is written. -- 2.53.0