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Sun, 08 Nov 2026 10:28:17 -0800 (PST) Received: from [192.168.1.100] ([163.245.50.16]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c4d6a47515dsm75254366b.44.2026.11.08.10.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 10:28:17 -0800 (PST) From: Alexander Letuchiy Date: Sun, 08 Nov 2026 21:27:10 +0300 Subject: [PATCH 1/2] dt-bindings: pinctrl: mediatek: Document MT6895 pin controller X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261108-pinctrl-mt6895-v1-1-f704c443b31a@gmail.com> References: <20261108-pinctrl-mt6895-v1-0-f704c443b31a@gmail.com> In-Reply-To: <20261108-pinctrl-mt6895-v1-0-f704c443b31a@gmail.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Alexander Letuchiy , Sean Wang Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org X-Mailer: b4 0.15.2 Add device tree bindings for the pin controller found in the MediaTek Dimensity 8000/8100 (MT6895) SoC. The controller has 227 GPIOs spread over a GPIO base and 13 IOCFG blocks, and an EINT controller made of five blocks (W, E, S, N, C). Pins with PUPD/R1/R0 or RSEL pull-ups take the raw MTK_PUPD_SET_R1R0_* and MTK_PULL_SET_RSEL_* values in bias-pull-up and bias-pull-down. There is no public table of the RSEL resistances for this SoC, so the binding does not offer the ohm-based values used on MT8188 and MT8195. Signed-off-by: Alexander Letuchiy --- .../bindings/pinctrl/mediatek,mt6895-pinctrl.yaml | 228 +++++++++++++++++++++ 1 file changed, 228 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6895-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6895-pinctrl.yaml new file mode 100644 index 000000000000..e3ecfffc084e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6895-pinctrl.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6895-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6895 Pin Controller + +maintainers: + - Alexander Letuchiy + +description: + The MediaTek MT6895 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6895-pinctrl + + reg: + items: + - description: pin controller base + - description: rm group IO + - description: rt group IO + - description: rmm group IO + - description: bl group IO + - description: bm group IO + - description: br group IO + - description: brr group IO + - description: lb group IO + - description: lm group IO + - description: rtt group IO + - description: tr group IO + - description: tl group IO + - description: lt group IO + - description: EINT controller W block + - description: EINT controller E block + - description: EINT controller S block + - description: EINT controller N block + - description: EINT controller C block + + reg-names: + items: + - const: base + - const: rm + - const: rt + - const: rmm + - const: bl + - const: bm + - const: br + - const: brr + - const: lb + - const: lm + - const: rtt + - const: tr + - const: tl + - const: lt + - const: eint-w + - const: eint-e + - const: eint-s + - const: eint-n + - const: eint-c + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: + maxItems: 247 + + interrupts: + description: EINT controller interrupt + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux are defined as macros in + arch/arm64/boot/dts/mediatek/mt6895-pinfunc.h for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) + #define PINMUX_GPIO6__FUNC_SCL0 (MTK_PIN_NO(6) | 1) + #define PINMUX_GPIO7__FUNC_SDA0 (MTK_PIN_NO(7) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6895-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x1000>, + <0x11c30000 0x1000>, + <0x11c40000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11d50000 0x1000>, + <0x11d60000 0x1000>, + <0x11e10000 0x1000>, + <0x11ea0000 0x1000>, + <0x11eb0000 0x1000>, + <0x11f20000 0x1000>, + <0x11f30000 0x1000>, + <0x11e50000 0x1000>, + <0x11ce0000 0x1000>, + <0x11de0000 0x1000>, + <0x11fe0000 0x1000>, + <0x1c01e000 0x1000>; + reg-names = "base", "rm", "rt", "rmm", "bl", "bm", "br", + "brr", "lb", "lm", "rtt", "tr", "tl", "lt", + "eint-w", "eint-e", "eint-s", "eint-n", "eint-c"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 227>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + gpio-pins { + pins { + pinmux = ; + bias-pull-up; + drive-strength = <6>; + }; + }; + + i2c0-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + }; -- 2.56.0