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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 5614622812f47-56813ac6352sm3570841b6e.1.2026.11.08.21.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 21:02:40 -0800 (PST) From: James Hilliard Date: Sun, 08 Nov 2026 22:02:36 -0700 Subject: [PATCH 1/3] dmaengine: dw-axi-dmac: poll the correct enable bit during termination X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261108-submit-dw-axi-dma-stop-pause-v1-v1-1-c48ec19e9ee4@gmail.com> References: <20261108-submit-dw-axi-dma-stop-pause-v1-v1-0-c48ec19e9ee4@gmail.com> In-Reply-To: <20261108-submit-dw-axi-dma-stop-pause-v1-v1-0-c48ec19e9ee4@gmail.com> To: Eugeniy Paltsev , Vinod Koul , Frank Li , Sergey Khimich , Andy Shevchenko , Sia Jee Heng Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, James Hilliard , stable@vger.kernel.org X-Mailer: b4 0.15.2 For channels 16 through 31, the channel enable bits occupy bits 32 through 47 of the extended DMAC_CHEN register. dma_chan_terminate_all() only reads the low word and tests BIT(chan->id), so it can conclude that an upper-bank channel has stopped while its actual enable bit remains set. Descriptors can then be freed while hardware still owns them. Poll axi_chan_is_hw_enable(), which already handles both register banks and the smaller channel layouts, instead of constructing another mask. Fixes: 495e18b16e3d ("dmaengine: dw-axi-dmac: Add support DMAX_NUM_CHANNELS > 16") Cc: stable@vger.kernel.org Signed-off-by: James Hilliard --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 7520c78f55cc..49f65486e862 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1181,16 +1181,15 @@ static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id) static int dma_chan_terminate_all(struct dma_chan *dchan) { struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); - u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT; unsigned long flags; - u32 val; + bool enabled; int ret; LIST_HEAD(head); axi_chan_disable(chan); - ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val, - !(val & chan_active), 1000, 50000); + ret = read_poll_timeout_atomic(axi_chan_is_hw_enable, enabled, !enabled, + 1000, 50000, false, chan); if (ret == -ETIMEDOUT) dev_warn(dmaengine_chan_dev(dchan), "%s failed to stop\n", axi_chan_name(chan)); -- 2.53.0