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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-7170f8fbc55sm1908138eaf.12.2026.11.08.13.23.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 13:23:54 -0800 (PST) From: James Hilliard Date: Sun, 08 Nov 2026 14:23:22 -0700 Subject: [PATCH 1/2] mtd: rawnand: macronix: serialize OTP access with NAND operations X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261108-submit-rawnand-operation-locking-v1-v1-1-565010fc5f8b@gmail.com> References: <20261108-submit-rawnand-operation-locking-v1-v1-0-565010fc5f8b@gmail.com> In-Reply-To: <20261108-submit-rawnand-operation-locking-v1-v1-0-565010fc5f8b@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Arseniy Krasnov , Boris Brezillon , Kyle Roeschley Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, James Hilliard , stable@vger.kernel.org X-Mailer: b4 0.15.2 The Macronix OTP callbacks select a target and issue feature and page commands without taking the chip or controller locks. Normal NAND I/O can interleave with these commands, use a different target or access pages while OTP mode is enabled. OTP I/O can also run while the chip is suspended. Make the existing NAND serialization helpers available within the raw NAND core and hold them across the entire OTP transaction, including restoring normal mode and deselecting the target. This uses the same lock ordering and suspend handling as normal NAND I/O. Fixes: e87161321a40 ("mtd: rawnand: macronix: OTP access for MX30LFxG18AC") Cc: stable@vger.kernel.org Cc: Arseniy Krasnov Signed-off-by: James Hilliard --- drivers/mtd/nand/raw/internals.h | 2 ++ drivers/mtd/nand/raw/nand_base.c | 4 ++-- drivers/mtd/nand/raw/nand_macronix.c | 2 ++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/internals.h b/drivers/mtd/nand/raw/internals.h index b8b29341b88c..2668f527e637 100644 --- a/drivers/mtd/nand/raw/internals.h +++ b/drivers/mtd/nand/raw/internals.h @@ -81,6 +81,8 @@ extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct mtd_pairing_scheme dist3_pairing_scheme; /* Core functions */ +void nand_get_device(struct nand_chip *chip); +void nand_release_device(struct nand_chip *chip); const struct nand_manufacturer_desc *nand_get_manufacturer_desc(u8 id); int nand_bbm_get_next_page(struct nand_chip *chip, int page); int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs); diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index a5b278ab9384..f125c529c62d 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -207,7 +207,7 @@ EXPORT_SYMBOL_GPL(nand_deselect_target); * * Release chip lock and wake up anyone waiting on the device. */ -static void nand_release_device(struct nand_chip *chip) +void nand_release_device(struct nand_chip *chip) { /* Release the controller and the chip */ mutex_unlock(&chip->controller->lock); @@ -336,7 +336,7 @@ static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs) * * Lock the device and its controller for exclusive access */ -static void nand_get_device(struct nand_chip *chip) +void nand_get_device(struct nand_chip *chip) { /* Wait until the device is resumed. */ while (1) { diff --git a/drivers/mtd/nand/raw/nand_macronix.c b/drivers/mtd/nand/raw/nand_macronix.c index 03237310852c..4fe7036ae992 100644 --- a/drivers/mtd/nand/raw/nand_macronix.c +++ b/drivers/mtd/nand/raw/nand_macronix.c @@ -380,6 +380,7 @@ static int __macronix_30lfxg18ac_rw_otp(struct mtd_info *mtd, int ret; nand = mtd_to_nand(mtd); + nand_get_device(nand); nand_select_target(nand, 0); ret = macronix_30lfxg18ac_otp_enable(nand); @@ -426,6 +427,7 @@ static int __macronix_30lfxg18ac_rw_otp(struct mtd_info *mtd, write ? "write" : "read"); nand_deselect_target(nand); + nand_release_device(nand); return ret; } -- 2.53.0