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Sun, 08 Nov 2026 05:18:32 -0800 (PST) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b3757214cbsm5336980c88.13.2026.11.08.05.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 05:18:32 -0800 (PST) From: Imran Shaik Subject: [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Date: Sun, 08 Nov 2026 18:48:21 +0530 Message-Id: <20261108-tscss-v2-0-d5f575010427@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAJ528GoC/0XO3YrDIBCG4VsJHq/FMRqzOep9LCWoM2mFbU01C buU3vtOf2BPhE+Gh/cmKpVEVQzNTRTaUk35wkN/NCKe/OVIMiFvoZXulFNWLjXWKo0B7I2JQOQ E386FpvTzdL4OvE+pLrn8PtkNHr9vQbu3sIFUMhAhGHLagtrnWnfX1X/HfD7v+BGH+0sudF05b Hnx/12cySaAcvIY45h0HNke6zrPuSyyM963VmMbAAeOYCz4SvLhp2VoECeyEJRXk8X4SQZsjDr 2HnsM4GyrEY3uAnfc/wA0kiO4KAEAAA== X-Change-ID: 20260705-tscss-441d844c1ee7 To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Bjorn Andersson , Konrad Dybcio , Eric Dumazet , Abel Vesa , Eric Dumazet Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Imran Shaik X-Mailer: b4 0.15.2 X-Proofpoint-ORIG-GUID: cChA9toulBtJBop9H0a1yoMZQ61Ol8MC X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA4MDA1MiBTYWx0ZWRfXw4Nkoio9XVg+ YsoyTytbw+kMnmYKicAZWl/EtNvGQAYxKQdSMkt3TaVkDzTSxQfQMIMqjcbJP+EQq8kPsr8BOyO ZgBQDkZcGssapyievswOKftoBQ5HL7s= X-Authority-Analysis: v=2.4 cv=dZMVTnXe c=1 sm=1 tr=0 ts=6af076aa cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=J1Y8HTJGAAAA:8 a=20KFwNOVAAAA:8 a=CLs3rlwnB2RECI_rIAYA:9 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 a=y1Q9-5lHfBjTkpIzbSAN:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA4MDA1MiBTYWx0ZWRfX+j39v6cD2a9+ hlr+BTfj0hdbnDMgXJDa47OGs9emUxxKqxVq8a0wUzbO2InPrLfVaMOz8K8Gnm3wgHsIUUFHAFg Uar7hf08+h2PeuisF6q2/Ksc5jTJDOmhZp1BhkZ4hyr9/XB+25HVWRD7JTCctPeyB39mI0YZKfg WCfS4lr/PzXdAj+K9F0QRjXxdJvocd5KIuvmapOYrO5QG794Lv8u5ZpSS8BsNV7G4L66bGTrrhr hA+mFYRheR7PxVBvVHlEITecVE8EgSYExCuKCjaq3ZV+8opsxLPNMO/5hVIcsT0YvbxMKD7eMwP vFdQX1BwQM+taBRu4Y2H141v1Ln3GViy2UZjdQtVEha1Ohpcn/3nZ4c3mvnUqDNEu8GgY3Lws+V GpR9lHoQfeHXNrcs7KvxbFO619RPigsj7OLdu/J7DoN2bEb5ZHCDrmtjNUbSvw6vRggVW1TDJHX GAH1d4I498PUPf7+DxQ== X-Proofpoint-GUID: cChA9toulBtJBop9H0a1yoMZQ61Ol8MC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-08_04,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 spamscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611080052 This series introduces support for the Qualcomm Timestamp Counter Subsystem (TSCSS) hardware, a time synchronization subsystem present on Qualcomm Lemans, Monaco and QDU1000 SoCs. TSCSS is composed of two main hardware blocks: - Timestamp Counter (TSC): a free-running hardware counter that provides continuous timekeeping for the SoC, and is functional with a GCC TSC AHB config clock and a global counter clock. The TSC counter resolution and supported functionalities vary across SoC variants. - Event Timestamp Unit (ETU): It captures TSC counter timestamps against external hardware events. Each ETU slice binds a slice identifier to an external event selector, and the ETU additionally requires its own clock, pinctrl along with either a per-slice interrupt (QDU1000) or a single summary interrupt across all ETU slices (Lemans and Monaco). +------------------------------------------------+ +------------------+ | Global clock controller - TSC AHB/CNTR/ETU CLK | | EVENT_IN[0:15] | +------------------------------------------------+ +------------------+ | | v v +----------------------------------------------------------------------+ | Timestamp Counter Subsystem (TSCSS) | | | | +----------------------------------------------+ | | +------------+ | Event Timestamp Unit (ETU) | | | | Timestamp | | 0x01C90000-0x01C9FFFF | | | | Counter | | +------------------------------------------+ | | | | (TSC) | | | ETU Slices | | | | | | | | [Slice 0] [Slice 1] [...] [Slice 15] | | | | | 0x1C80000 | | | 0x1C90000 0x1C91000 0x1C9F000 | | | | +------------+ | | | | | | | +-----------+------------------------------+ | | | +-------------|--------------------+-----------+ | | | | | +---------------------------------|--------------------|---------------+ | | v v +----------------------------------------+ | per-slice IRQ (OR) summary IRQ | | (QDU1000) (Lemans) | +----------------------------------------+ | v +-----------------------------+ | Interrupt Controller | +-----------------------------+ The address offsets shown in the diagram above are specific to Qualcomm Lemans SoC. The Qualcomm Nord SoC additionally has a timer register region used to generate a periodic pulse in sync with the TSC counter. This series currently covers only the TSC block driver functionality; ETU driver support will follow in a later series. Signed-off-by: Imran Shaik --- Changes in v2: - Fixed SoC names, and updated bindings as per review comments on v1 [Krzysztof] - Added ARCH_QCOM in Kconfig, fixed the probe() and remove() order, and used dev_err_probe [Krzysztof] - Dropped the unnecessary "inline" keyword [Jakub] - Added support for Nord and Shikra SoCs, which support continuous dynamic dynamic drift correction. - Updated the clocks handling. - Link to v1: https://lore.kernel.org/r/20260727-tscss-v1-0-beed14e72510@oss.qualcomm.com To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Richard Cochran To: Andrew Lunn To: "David S. Miller" To: Eric Dumazet To: Jakub Kicinski To: Paolo Abeni To: Bjorn Andersson To: Konrad Dybcio To: Abel Vesa Cc: Ajit Pandey Cc: Imran Shaik Cc: Taniya Das Cc: Jagadeesh Kona Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: netdev@vger.kernel.org --- Imran Shaik (10): dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs dt-bindings: ptp: Document TSCSS hardware on Qualcomm QDU1000 SoC dt-bindings: ptp: Document TSCSS hardware on Qualcomm Nord and Shikra SoCs ptp: qcom: Add PTP driver for the Qualcomm TSC hardware arm64: defconfig: Enable Qualcomm TSC driver arm64: dts: qcom: lemans: Add support for TSCSS node arm64: dts: qcom: monaco: Add support for TSCSS node arm64: dts: qcom: qdu1000: Add support for TSCSS node arm64: dts: qcom: shikra: Add support for TSCSS node arm64: dts: qcom: nord: Add support for TSCSS node .../devicetree/bindings/ptp/qcom,nord-tscss.yaml | 186 +++++++ .../bindings/ptp/qcom,qdu1000-tscss.yaml | 170 ++++++ .../bindings/ptp/qcom,sa8775p-tscss.yaml | 169 ++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 12 + arch/arm64/boot/dts/qcom/monaco.dtsi | 12 + arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 14 + arch/arm64/boot/dts/qcom/qdu1000.dtsi | 13 + arch/arm64/boot/dts/qcom/shikra.dtsi | 12 + arch/arm64/configs/defconfig | 1 + drivers/ptp/Kconfig | 11 + drivers/ptp/Makefile | 1 + drivers/ptp/ptp_qcom_tsc.c | 598 +++++++++++++++++++++ 12 files changed, 1199 insertions(+) --- base-commit: ddfe51b0a0f5dc9e415cc2c8ad8db17532dd426b change-id: 20260705-tscss-441d844c1ee7 prerequisite-change-id: 20261107-gcc_i2c_tsc_support-64aa352d3b1d:v1 prerequisite-patch-id: 8c93973348ea4b80f1dfcd445a8a3afb8a530d21 prerequisite-patch-id: 5a3418fa67b14fd6b67e00f8c21ee699fedb320d Best regards, -- Imran Shaik