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Miller" , Jakub Kicinski , Paolo Abeni , Bjorn Andersson , Konrad Dybcio , Eric Dumazet , Abel Vesa , Eric Dumazet Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Imran Shaik X-Mailer: b4 0.15.2 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA4MDA1MiBTYWx0ZWRfX7F9pFxI7hPju NJLhKqnPFTL8vacTkeSOcceU6jvGDPFNNhkB2lu16CZMqK2jFQQK1FkEXh2wXO20gsVkVPiqSrG UaHublq4E9jJ6BliTvqD+riLhI+pVFo= X-Proofpoint-GUID: NCT2RHk0UjNUygwBkINy_pQNtPLj52AP X-Authority-Analysis: v=2.4 cv=FrKQbGrq c=1 sm=1 tr=0 ts=6af076b0 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=nKCL-24MKaImGustjYoA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: NCT2RHk0UjNUygwBkINy_pQNtPLj52AP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA4MDA1MiBTYWx0ZWRfX4+qeg2/3RlM9 rcCT/vaps2IAELHSOywnOn2c8f4X4Q7U/ZpDM+D3xSdSzVJMyqeJkTMq/N9lhvvkMyTuhhEUdNV sXW7RCxGW/W63GiigbYXV/JodzXu+7YUmBzq2psSgvnFwK3OiWJGKWvAMfWXdLDolGRt40+QL6N Hz3+EbbMcyKgNRUAYh4lE0bnv8B+ZJFWPOgzpkB/ZR+nRiDO94/Lr4Zd0YBeqlfJV0qSM36JkOf 3wEQM/oVmGyXfKkurw+p+CNIzPZubkjqTNWOzbXSUH43e+MhDRhLoFrJH6TwIghnBtt1cvrPq5Z E/pjSmDGw+zGgJ70uFUT5XsmVrIpAErDRbjKj3ZV64WNOpqEuZfkIGCAq62x9r6oSMtwXWBi8G4 QRclQofXqStAIt5tmVtTfzO1kHYUnFdDtJXsmW2AeqpXGWCVpqZ8OpTsbhuoujW38NWfniaSwvF cjmEfQ2hGO1HLtg84yg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-08_04,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1011 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611080052 Add Devicetree bindings for the Timestamp Counter Subsystem (TSCSS) found on Qualcomm SA8775P and QCS8300 SoCs. TSCSS is a time synchronization subsystem composed of two main blocks: Timestamp Counter (TSC) and Event Timestamp Unit (ETU). The TSC block provides a continuously running counter used for timekeeping, while the ETU captures timestamps for external hardware event triggers. Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik --- .../bindings/ptp/qcom,sa8775p-tscss.yaml | 169 +++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/Documentation/devicetree/bindings/ptp/qcom,sa8775p-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,sa8775p-tscss.yaml new file mode 100644 index 000000000000..b3e3a7cd7166 --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/qcom,sa8775p-tscss.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ptp/qcom,sa8775p-tscss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Timestamp Counter Subsystem (TSCSS) on Qualcomm SA8775P and QCS8300 + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + Qualcomm TSCSS is a time synchronization subsystem composed of two main + blocks - the Timestamp Counter (TSC) and the Event Timestamp Unit (ETU). + + The TSC block is a timestamp generator that maintains a running counter used + for system timekeeping, and is functional with just the AHB and counter + clocks. + The ETU block captures TSC timestamps for external hardware events. Each + ETU slice binds a slice number to an external event selector, and a + single summary interrupt is raised for any ETU slice event. + +properties: + compatible: + oneOf: + - const: qcom,sa8775p-tscss + - items: + - const: qcom,qcs8300-tscss + - const: qcom,sa8775p-tscss + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: tsc + - const: etu + + clocks: + items: + - description: TSC AHB configuration clock. + - description: TSC global counter clock. + - description: TSC ETU clock. + + clock-names: + items: + - const: ahb + - const: cntr + - const: etu + + interrupts: + items: + - description: + Summary interrupt raised based on an external event for any + of the ETU slices. + + interrupt-names: + items: + - const: etu_summary + + pinctrl-names: + minItems: 1 + maxItems: 16 + items: + pattern: "^slice[0-9]+$" + + qcom,etu-slice: + description: + ETU slice number for each entry in pinctrl-, pinctrl-names and + qcom,etu-event-sel. + minItems: 1 + maxItems: 16 + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,etu-event-sel: + description: + External event selection value for each ETU slice listed in + qcom,etu-slice. + minItems: 1 + maxItems: 16 + $ref: /schemas/types.yaml#/definitions/uint32-array + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +allOf: + - if: + properties: + reg-names: + contains: + const: etu + then: + properties: + reg: + minItems: 2 + maxItems: 2 + required: + - interrupts + - interrupt-names + - pinctrl-names + - qcom,etu-slice + - qcom,etu-event-sel + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ptp@1c80000 { + compatible = "qcom,sa8775p-tscss"; + reg = <0x0 0x01c80000 0x0 0x2000>; + reg-names = "tsc"; + + clocks = <&gcc GCC_TSCSS_AHB_CLK>, + <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>, + <&gcc GCC_TSCSS_ETU_CLK>; + clock-names = "ahb", "cntr", "etu"; + + assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>; + assigned-clock-rates = <15625000>; + }; + }; + + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ptp@1c80000 { + compatible = "qcom,sa8775p-tscss"; + reg = <0x0 0x01c80000 0x0 0x2000>, + <0x0 0x01c90000 0x0 0x10000>; + reg-names = "tsc", "etu"; + + clocks = <&gcc GCC_TSCSS_AHB_CLK>, + <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>, + <&gcc GCC_TSCSS_ETU_CLK>; + clock-names = "ahb", "cntr", "etu"; + + assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>; + assigned-clock-rates = <15625000>; + + interrupts = ; + interrupt-names = "etu_summary"; + + pinctrl-0 = <&cci_timer0>; + pinctrl-1 = <&cci_timer1>; + pinctrl-names = "slice1", "slice2"; + + qcom,etu-slice = <1 2>; + qcom,etu-event-sel = <1 2>; + }; + }; +... -- 2.34.1