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Sun, 8 Nov 2026 08:23:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marcant.net; s=gandalf; t=1794122583; bh=iF3RZzWU8Se+cRJ7T9+DnW6N/jqKZYCmrKktze3/CIw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rjYxRW3pASk7MhXSwxWzzAGXCF+Vo0/6lTj2/f6KyGwBSeLmxSVouIdlwT+IL4N7Y cKoxLp33+LGzGFpWGu6Lf8FF1MBFN0pxp5tbSFR43xLMpeJC7+G54conQEfyZcznG2 ir2JNWz7eB9lcAqLl9iw0V5m5CyhAaPCPeRQVQXE= From: =?UTF-8?q?Andr=C3=A9=20Valentin?= To: Bjorn Andersson , Stephen Boyd Cc: Abel Vesa , Brian Masney , Jerome Brunet , Konrad Dybcio , Julius Bairaktaris , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Andr=C3=A9=20Valentin?= Subject: [PATCH 2/2] clk: qcom: gcc-ipq8074: keep port 5 on uniphy1 at SGMII rates Date: Sun, 8 Nov 2026 08:23:02 +0100 Message-ID: <20261108072302.2311227-3-avalentin@marcant.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261108072302.2311227-1-avalentin@marcant.net> References: <20261108072302.2311227-1-avalentin@marcant.net> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; 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The port 5 RX and TX frequency tables serve uniphy1 only at 312.5 MHz: 125 MHz lists uniphy1 / 2.5 and then uniphy0 / 1, 25 MHz lists uniphy1 / 12.5 and then uniphy0 / 5. __clk_rcg2_select_conf() takes the first config that gives the rate exactly, so once uniphy1 runs at 125 MHz, a 1G or 100M rate that reaches the RCG moves the port onto uniphy0 whenever uniphy0 runs at 125 MHz, and otherwise leaves it on uniphy1 at 50 MHz (1G) or 10 MHz (100M). Add uniphy1 / 1 to the 125 MHz configs and uniphy1 / 5 to the 25 MHz configs. They go after the existing uniphy1 entries, which serve uniphy1 at 312.5 MHz, so that 2500BASE-X keeps its divider, and before uniphy0. The port 6 tables already list uniphy2 / 1 and uniphy2 / 5 next to uniphy2 / 2.5 and uniphy2 / 12.5. Suggested-by: Julius Bairaktaris Signed-off-by: André Valentin --- drivers/clk/qcom/gcc-ipq8074.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 1329ea28d70..fb172b9aec0 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -1679,11 +1679,13 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = { static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = { C(P_UNIPHY1_RX, 12.5, 0, 0), + C(P_UNIPHY1_RX, 5, 0, 0), C(P_UNIPHY0_RX, 5, 0, 0), }; static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = { C(P_UNIPHY1_RX, 2.5, 0, 0), + C(P_UNIPHY1_RX, 1, 0, 0), C(P_UNIPHY0_RX, 1, 0, 0), }; @@ -1749,11 +1751,13 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = { static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = { C(P_UNIPHY1_TX, 12.5, 0, 0), + C(P_UNIPHY1_TX, 5, 0, 0), C(P_UNIPHY0_TX, 5, 0, 0), }; static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = { C(P_UNIPHY1_TX, 2.5, 0, 0), + C(P_UNIPHY1_TX, 1, 0, 0), C(P_UNIPHY0_TX, 1, 0, 0), }; -- 2.47.3