From: David Laight <david.laight.linux@gmail.com>
To: Yunhui Cui <cuiyunhui@bytedance.com>
Cc: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, dennis@kernel.org, tj@kernel.org, cl@gentwo.org,
ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org,
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broonie@kernel.org
Subject: Re: [PATCH v9 1/3] riscv: implement this_cpu operations
Date: Sun, 8 Nov 2026 21:32:54 +0000 [thread overview]
Message-ID: <20261108213254.67805ef0@pumpkin> (raw)
In-Reply-To: <20261108110406.97495-2-cuiyunhui@bytedance.com>
On Sun, 8 Nov 2026 19:04:04 +0800
Yunhui Cui <cuiyunhui@bytedance.com> wrote:
> RISC-V has no asm/percpu.h, so this_cpu_*() read-modify-write
> operations use generic implementations that disable local interrupts.
>
> Implement RISC-V-specific this_cpu operations with preemption disabled
> to keep accesses on the current CPU.
Have you looked at some of the schemes (I think arm64 has the latest,
but also s390) that do most per-cpu ops without disabling preemption.
In particular they save the pre-emption check when pre-emption
is enabled.
Basically the code tells the scheduler which register contains the
per-cpu data so that it can be 'magically' flipped during a context
switch.
David
next prev parent reply other threads:[~2026-11-08 21:32 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-08 11:04 [PATCH v9 0/3] riscv: optimize percpu access Yunhui Cui
2026-11-08 11:04 ` [PATCH v9 1/3] riscv: implement this_cpu operations Yunhui Cui
2026-11-08 11:58 ` bot+bpf-ci
2026-11-08 21:32 ` David Laight [this message]
2026-11-08 11:04 ` [PATCH v9 2/3] riscv: store percpu offset into thread_info Yunhui Cui
2026-11-08 11:04 ` [PATCH v9 3/3] riscv: select HAVE_CMPXCHG_LOCAL Yunhui Cui
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