From: Pufan Jin <cyan2254650260@gmail.com>
To: Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Michal Simek <michal.simek@amd.com>,
Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 0/2] ARM: dts: zynq: Add ALINX AX7Z020B development board
Date: Mon, 9 Nov 2026 05:50:08 +0800 [thread overview]
Message-ID: <20261108215010.351256-1-cyan2254650260@gmail.com> (raw)
This series adds device tree support for the ALINX AX7Z020B development
board, based on the Xilinx Zynq-7000 SoC (XC7Z020-2CLG400I).
Note: the "alinx" vendor prefix is not part of this series, it is already
present as commit 1f06cd374a60 ("dt-bindings: vendor-prefixes: Add ALINX
vendor prefix") in the Xilinx for-next branch.
The platform consists of two physical layers:
1. ALINX AC7Z020 system on module (SoM), in zynq-alinx-ac7z020.dtsi:
- Xilinx XC7Z020-2CLG400I SoC (dual ARM Cortex-A9, 33.333333MHz PS_CLK)
- 1024 MiB DDR3 SDRAM (2x MT41K256M16RE-125, 32-bit bus)
- 32 MiB QSPI Flash (Winbond W25Q256FVEI) with 4 MTD partitions
- DevCFG FPGA manager
2. The AX7Z020B board (AC7Z020 SoM plus carrier board), described in
zynq-alinx-ax7z020b.dts:
- Serial console via USB-UART bridge (CP2102, MIO 48-49)
- MicroSD slot on SDHCI0 (MIO 40-45)
- Gigabit Ethernet via GEM0 (MIO 16-27 RGMII, MIO 52-53 MDIO)
with JLSemi JL2121 PHY at MDIO address 1 and RJ45 link/activity LEDs
- USB 2.0 host via USB3320C ULPI PHY (MIO 28-39), reset on MIO 46
- Dual CAN buses (CAN0 on MIO 10-11, CAN1 on MIO 12-13) with
SN65HVD232 transceivers
- I2C bus on MIO 50-51 with 24LC04 EEPROM, DS1338 RTC and LM75 sensor
- 2x SMA AD inputs and a spare differential pair wired to XADC aux
channels VAUX1/VAUX9/VAUX12. XADC is a hard macro accessible from the
PS without PL configuration, the channels are enabled via the
xlnx,channels property.
Tested on hardware: boot from SD card, UART console, SD card, GbE with
iperf3 (940+ Mbps) and netdev LED trigger hardware offload, USB host,
dual CAN (SocketCAN at 500 kbps), I2C sensors, QSPI flash MTD partitions,
and XADC temperature/voltage plus the external AD aux channels via IIO.
The DTB passes CHECK_DTBS=y and the bindings pass dt_binding_check.
Pufan Jin (2):
dt-bindings: soc: xilinx: Add ALINX AX7Z020B board
ARM: dts: zynq: Add ALINX AX7Z020B development board
.../bindings/soc/xilinx/xilinx.yaml | 6 +
arch/arm/boot/dts/xilinx/Makefile | 1 +
.../boot/dts/xilinx/zynq-alinx-ac7z020.dtsi | 72 +++++++++
.../boot/dts/xilinx/zynq-alinx-ax7z020b.dts | 137 ++++++++++++++++++
4 files changed, 216 insertions(+)
create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
--
2.56.0
next reply other threads:[~2026-11-08 21:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-08 21:50 Pufan Jin [this message]
2026-11-08 21:50 ` [PATCH 1/2] dt-bindings: soc: xilinx: Add ALINX AX7Z020B board Pufan Jin
2026-11-08 21:50 ` [PATCH 2/2] ARM: dts: zynq: Add ALINX AX7Z020B development board Pufan Jin
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