[PATCH 2/2] serial: 8250_dw: Select U6_16550A for 64-byte FIFO

["Kryštof Černý via B4 Relay" <devnull+cleverline1mc.gmail.com@kernel.org>]

From: Kryštof Černý <cleverline1mc@gmail.com>

DesignWare 8250 ports that describe their FIFO in the CPR register are
always configured as PORT_16550A, regardless of the FIFO depth. On
UARTs with a 64-byte FIFO, such as those on the Rockchip RK3328, this
selects the 16-byte rxtrig_bytes table {1, 4, 8, 14}. The rx_trig_bytes
sysfs attribute then reports 8 bytes while the hardware triggers at 32,
and writes to it program the wrong trigger level.

Select PORT_U6_16550A when the CPR reports a 64-byte FIFO. Generic
autoconfig already assigns this type to a 16550A with a 64-byte FIFO,
and its rxtrig_bytes table matches the DesignWare FCR RT encoding.

The FIFO size, TX load size and capabilities are still taken from the
CPR, and the default FCR value is the same for both types, so the
hardware is programmed exactly as before. The port type reported to
userspace changes from 16550A to U6_16550A.

Co-developed-by: Miroslav Ondra <ondra@faster.cz>
Signed-off-by: Miroslav Ondra <ondra@faster.cz>
Signed-off-by: Kryštof Černý <cleverline1mc@gmail.com>
---
 drivers/tty/serial/8250/8250_dwlib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c
index 9bb02a4ab11f..ae556b06b03a 100644
--- a/drivers/tty/serial/8250/8250_dwlib.c
+++ b/drivers/tty/serial/8250/8250_dwlib.c
@@ -236,9 +236,9 @@ void dw8250_setup_port(struct uart_port *p)
 
 	/* Select the type based on FIFO */
 	if (reg & DW_UART_CPR_FIFO_MODE) {
-		p->type = PORT_16550A;
 		p->flags |= UPF_FIXED_TYPE;
 		p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
+		p->type = (p->fifosize == 64) ? PORT_U6_16550A : PORT_16550A;
 		up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT;
 	}
 

-- 
2.47.3