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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-718a945ceebsm717268eaf.8.2026.11.09.18.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 18:11:38 -0800 (PST) From: Enzo Adriano To: linusw@kernel.org, wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org Cc: Andre Przywara , Vinicius Pedrosa , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3] pinctrl: sunxi: use automatic voltage detection on A733 Date: Mon, 9 Nov 2026 21:11:36 -0500 Message-ID: <20261109-a733-pinctrl-v3@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit A733 uses two-bit voltage-mode fields, but the handlers selected when v7.4-rc1 added A733 support program them as one-bit fields. The R-PIO handler also writes an A523 control register absent on A733. Add BIAS_VOLTAGE_PIO_POW_AUTO to select auto (01) in every field of POW_MOD_SEL at controller init and skip per-pin voltage setup. Use it for both A733 controllers: the A733 User Manual v1.00 documents 01 as auto in sections 18.14.6.1 and 18.14.7.20. Give A733-R a separate descriptor so A523-R keeps its existing voltage handling. Fixes: 0535bfbfa97b ("pinctrl: sunxi: add support for the Allwinner A733") Fixes: 31d68e10381c ("pinctrl: sunxi: a523-r: add a733-r compatible string") Link: https://lore.kernel.org/r/20261107000135.6b684277@ryzen.lan Suggested-by: Andre Przywara Suggested-by: Vinicius Pedrosa Signed-off-by: Enzo Adriano --- Changes in v3: - Set every two-bit field to AUTO at init on both A733 controllers. - Shorten the description; retain A523-R's existing handling. - Drop Vinicius' Tested-by because the voltage-mode programming changed. Keep his Suggested-by for the separate A733-R descriptor. v2: https://lore.kernel.org/r/20261104-a733-pinctrl-v2@gmail.com Replaces Andre's RFT: https://lore.kernel.org/r/20261013142351.771229-1-andre.przywara@arm.com Tests: arm64 defconfig sunxi W=1, boot-stack Image W=1 and DTB W=2 built. Not tested: board boot, 1.8 V switching, A523. drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 19 +++++++++++++++---- drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 ++++++- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 ++ 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c index cffc1e53eef1..006754c0645f 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -30,17 +30,28 @@ static struct sunxi_pinctrl_desc a523_r_pinctrl_data = { .pin_base = PL_BASE, }; +static struct sunxi_pinctrl_desc a733_r_pinctrl_data = { + .irq_banks = ARRAY_SIZE(a523_r_irq_bank_map), + .irq_bank_map = a523_r_irq_bank_map, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_AUTO, + .pin_base = PL_BASE, +}; + static int a523_r_pinctrl_probe(struct platform_device *pdev) { + struct sunxi_pinctrl_desc *desc; + + desc = (struct sunxi_pinctrl_desc *)of_device_get_match_data(&pdev->dev); return sunxi_pinctrl_dt_table_init(pdev, a523_r_nr_bank_pins, - a523_r_irq_bank_muxes, - &a523_r_pinctrl_data, + a523_r_irq_bank_muxes, desc, SUNXI_PINCTRL_NCAT2_REG_LAYOUT); } static const struct of_device_id a523_r_pinctrl_match[] = { - { .compatible = "allwinner,sun55i-a523-r-pinctrl", }, - { .compatible = "allwinner,sun60i-a733-r-pinctrl", }, + { .compatible = "allwinner,sun55i-a523-r-pinctrl", + .data = &a523_r_pinctrl_data }, + { .compatible = "allwinner,sun60i-a733-r-pinctrl", + .data = &a733_r_pinctrl_data }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c index ca82f08a3a65..e095abbb7232 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c @@ -24,7 +24,7 @@ static const u8 a733_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = static struct sunxi_pinctrl_desc a733_pinctrl_data = { .irq_banks = 10, .irq_read_needs_mux = true, - .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_AUTO, }; static int a733_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 3ee5012463da..444930d3c389 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -732,7 +732,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, u32 val, reg; int uV; - if (!pctl->desc->io_bias_cfg_variant) + if (pctl->desc->io_bias_cfg_variant == BIAS_VOLTAGE_NONE || + pctl->desc->io_bias_cfg_variant == BIAS_VOLTAGE_PIO_POW_AUTO) return 0; uV = regulator_get_voltage(supply); @@ -1659,6 +1660,10 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, if (IS_ERR(clk)) return PTR_ERR(clk); + /* Select auto (01) for every bank, including shared VCC-IO. */ + if (desc->io_bias_cfg_variant == BIAS_VOLTAGE_PIO_POW_AUTO) + writel(0x55555555, pctl->membase + pctl->pow_mod_sel_offset); + /* * Seed the output latch shadow from the hardware so pins the * bootloader left in output mode keep their state; see diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 7c2f29e75519..7b36c5c2263e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -130,6 +130,8 @@ enum sunxi_desc_bias_voltage { */ BIAS_VOLTAGE_PIO_POW_MODE_CTL, BIAS_VOLTAGE_PIO_POW_MODE_CTL_INV, + /* Two-bit PIO_POW_MOD_SEL fields set to automatic voltage detection. */ + BIAS_VOLTAGE_PIO_POW_AUTO, }; struct sunxi_desc_function { base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.53.0