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CCI v1.2 introduces burst mode support, where consecutive write commands (marked as burst) run back-to-back as a single transfer. Use this in cci_i2c_write() to allow longer writes across the whole queue instead of a single command's payload, and raise max_write_len accordingly for every CCI revision that supports burst mode. unlock/lock commands are required to ensure the commands for a given transfer are executed atomically. Reviewed-by: Konrad Dybcio Signed-off-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c index 48dabd923b690864eccc29d232847c80f3c3b46c..a698130f4712492847336e401c0789b1a64dd02e 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -87,14 +87,24 @@ #define NUM_QUEUES 2 #define CCI_I2C_SET_PARAM 1 +#define CCI_I2C_LOCK 6 +#define CCI_I2C_UNLOCK 7 #define CCI_I2C_REPORT 8 #define CCI_I2C_WRITE 9 #define CCI_I2C_READ 10 +#define CCI_I2C_REPORT_IRQ_EN BIT(8) + #define CCI_I2C_WRITE_WC 3 +#define CCI_I2C_WRITE_MAX_LEN (CCI_I2C_WRITE_WC * sizeof(u32) - 1) #define CCI_I2C_WRITE_NWORDS(len) DIV_ROUND_UP((len) + 1, sizeof(u32)) +#define CCI_I2C_WRITE_BURST 0xf +#define CCI_I2C_BURST_OVERHEAD 4 /* LOCK + SET_PARAM + UNLOCK + REPORT */ -#define CCI_I2C_REPORT_IRQ_EN BIT(8) +/* Largest write that can be bursted through a queue of @qsize words */ +#define CCI_I2C_BURST_MAX_LEN(qsize) \ + (((qsize) - CCI_I2C_BURST_OVERHEAD) / CCI_I2C_WRITE_WC * \ + CCI_I2C_WRITE_MAX_LEN) enum { I2C_MODE_STANDARD, @@ -516,11 +526,11 @@ static int cci_i2c_read(struct cci *cci, u16 master, return 0; } -static void cci_i2c_load_write(u8 *buf, u16 len, void __iomem *loadq) +static void cci_i2c_load_write(void __iomem *loadq, u8 *buf, u16 len, bool burst) { u32 cmd[CCI_I2C_WRITE_WC] = { }; - cmd[0] = CCI_I2C_WRITE | len << 4; + cmd[0] = CCI_I2C_WRITE | (burst ? CCI_I2C_WRITE_BURST : len) << 4; memcpy((u8 *)cmd + 1, buf, len); iowrite32_rep(loadq, cmd, CCI_I2C_WRITE_NWORDS(len)); } @@ -529,6 +539,7 @@ static int cci_i2c_write(struct cci *cci, u16 master, u16 addr, u8 *buf, u16 len) { void __iomem *loadq = cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, QUEUE_0); + bool burst = len > CCI_I2C_WRITE_MAX_LEN; int ret; u32 val; @@ -546,10 +557,22 @@ static int cci_i2c_write(struct cci *cci, u16 master, if (ret < 0) return ret; + if (burst) + writel(CCI_I2C_LOCK, loadq); + val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4; writel(val, loadq); - cci_i2c_load_write(buf, len, loadq); + do { + u16 to_write = min_t(u16, len, CCI_I2C_WRITE_MAX_LEN); + + len -= to_write; + cci_i2c_load_write(loadq, buf, to_write, len > 0); + buf += to_write; + } while (len); + + if (burst) + writel(CCI_I2C_UNLOCK, loadq); val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN; writel(val, loadq); @@ -719,7 +742,7 @@ static const struct cci_data cci_hw_catalog[] = { .max_mode = I2C_MODE_FAST_PLUS, .queue_size = { 64, 16 }, .quirks = { - .max_write_len = 11, + .max_write_len = CCI_I2C_BURST_MAX_LEN(64), .max_read_len = 12, }, }, @@ -728,7 +751,7 @@ static const struct cci_data cci_hw_catalog[] = { .max_mode = I2C_MODE_FAST_PLUS, .queue_size = { 128, 32 }, .quirks = { - .max_write_len = 11, + .max_write_len = CCI_I2C_BURST_MAX_LEN(128), .max_read_len = 12, }, }, @@ -737,7 +760,7 @@ static const struct cci_data cci_hw_catalog[] = { .max_mode = I2C_MODE_FAST_PLUS, .queue_size = { 128, 32 }, .quirks = { - .max_write_len = 11, + .max_write_len = CCI_I2C_BURST_MAX_LEN(128), .max_read_len = 12, }, }, @@ -746,7 +769,7 @@ static const struct cci_data cci_hw_catalog[] = { .max_mode = I2C_MODE_FAST_PLUS, .queue_size = { 1024, 32 }, .quirks = { - .max_write_len = 11, + .max_write_len = CCI_I2C_BURST_MAX_LEN(1024), .max_read_len = 12, }, }, -- 2.34.1