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Sun, 08 Nov 2026 16:28:50 -0800 (PST) Received: from [192.168.10.105] ([212.58.121.92]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49673b94dc1sm2688388f8f.16.2026.11.08.16.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 16:28:48 -0800 (PST) From: Stanislav Aleksandrov Date: Mon, 09 Nov 2026 00:28:38 +0000 Subject: [PATCH 2/2] pinctrl: qcom: Add Halliday pinctrl driver X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261109-halliday-tlmm-v1-2-a181d54214cd@gmail.com> References: <20261109-halliday-tlmm-v1-0-a181d54214cd@gmail.com> In-Reply-To: <20261109-halliday-tlmm-v1-0-a181d54214cd@gmail.com> To: Bartosz Golaszewski , Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stanislav Aleksandrov X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794184120; l=61370; i=lightofmysoul@gmail.com; s=20261108; h=from:subject:message-id; bh=ZdTwOva7hVOm+Tf07L+Z3uVZTU2rseEzuM+nZWUxTDc=; b=wNOv9oDy0Bqh+E/CyOk6DOP5ATqTU42GV6nEd3tsIfzvQOr6OCUXVB2WKSYPBSvasyNyYtz3W phKjOhhPrexAr7+rEeFIO8jGDpwbTDzhR5thH65cl7FHnH4akzsgqbl X-Developer-Key: i=lightofmysoul@gmail.com; a=ed25519; pk=jeRUlfmkhE53CJPoeIIXgu7rTE0ybDRH0HQrEwbydzg= Add the pinctrl driver for the TLMM block found in the Qualcomm Halliday SoC: 224 GPIOs with their functions and PDC wakeup interrupts, the UFS reset pin and the SDC2 pins. The tables are based on Qualcomm's downstream pinctrl-anorak driver. Signed-off-by: Stanislav Aleksandrov --- drivers/pinctrl/qcom/Kconfig.msm | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-halliday.c | 1825 +++++++++++++++++++++++++++++++ 3 files changed, 1836 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index e45c701db627..2d470783bfe1 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -39,6 +39,16 @@ config PINCTRL_GLYMUR Say Y here to compile statically, or M here to compile it as a module. If unsure, say N. +config PINCTRL_HALLIDAY + tristate "Qualcomm Halliday pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc Halliday platform + (SXR2250P / Snapdragon XR2+ Gen 2). + config PINCTRL_HAWI tristate "Qualcomm Hawi pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index a3daca77a448..c2b3cb284faa 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o +obj-$(CONFIG_PINCTRL_HALLIDAY) += pinctrl-halliday.o obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o obj-$(CONFIG_PINCTRL_HAWI_LPASS_LPI) += pinctrl-hawi-lpass-lpi.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o diff --git a/drivers/pinctrl/qcom/pinctrl-halliday.c b/drivers/pinctrl/qcom/pinctrl-halliday.c new file mode 100644 index 000000000000..cc179c91cea0 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-halliday.c @@ -0,0 +1,1825 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2026, Stanislav Aleksandrov + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc halliday_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "GPIO_217"), + PINCTRL_PIN(218, "GPIO_218"), + PINCTRL_PIN(219, "GPIO_219"), + PINCTRL_PIN(220, "GPIO_220"), + PINCTRL_PIN(221, "GPIO_221"), + PINCTRL_PIN(222, "GPIO_222"), + PINCTRL_PIN(223, "GPIO_223"), + PINCTRL_PIN(224, "UFS_RESET"), + PINCTRL_PIN(225, "SDC2_CLK"), + PINCTRL_PIN(226, "SDC2_CMD"), + PINCTRL_PIN(227, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); +DECLARE_MSM_GPIO_PINS(217); +DECLARE_MSM_GPIO_PINS(218); +DECLARE_MSM_GPIO_PINS(219); +DECLARE_MSM_GPIO_PINS(220); +DECLARE_MSM_GPIO_PINS(221); +DECLARE_MSM_GPIO_PINS(222); +DECLARE_MSM_GPIO_PINS(223); + +static const unsigned int ufs_reset_pins[] = { 224 }; +static const unsigned int sdc2_clk_pins[] = { 225 }; +static const unsigned int sdc2_cmd_pins[] = { 226 }; +static const unsigned int sdc2_data_pins[] = { 227 }; + +enum halliday_functions { + msm_mux_gpio, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk0, + msm_mux_audio_ext_mclk1, + msm_mux_audio_ref_clk, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp0_hot, + msm_mux_edp0_hot, + msm_mux_edp0_lcd_self, + msm_mux_edp1_dpu0_lcd, + msm_mux_edp1_dpu1_lcd, + msm_mux_edp1_hot, + msm_mux_gcc_gp1, + msm_mux_gcc_gp10, + msm_mux_gcc_gp11, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_gp4, + msm_mux_gcc_gp5, + msm_mux_gcc_gp6, + msm_mux_gcc_gp7, + msm_mux_gcc_gp8, + msm_mux_gcc_gp9, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_i2s2_data0, + msm_mux_i2s2_data1, + msm_mux_i2s2_sck, + msm_mux_i2s2_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp0_vsync, + msm_mux_mdp0_vsync0_out, + msm_mux_mdp0_vsync1_out, + msm_mux_mdp0_vsync2_out, + msm_mux_mdp0_vsync3_out, + msm_mux_mdp0_vsync4_out, + msm_mux_mdp0_vsync5_out, + msm_mux_mdp0_vsync6_out, + msm_mux_mdp0_vsync7_out, + msm_mux_mdp0_vsync8_out, + msm_mux_mdp1_vsync, + msm_mux_mdp1_vsync0_out, + msm_mux_mdp1_vsync1_out, + msm_mux_mdp1_vsync2_out, + msm_mux_mdp1_vsync3_out, + msm_mux_mdp1_vsync4_out, + msm_mux_mdp1_vsync5_out, + msm_mux_mdp1_vsync6_out, + msm_mux_mdp1_vsync7_out, + msm_mux_mdp1_vsync8_out, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie2_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_pwm_0, + msm_mux_pwm_1, + msm_mux_pwm_10, + msm_mux_pwm_11, + msm_mux_pwm_12, + msm_mux_pwm_13, + msm_mux_pwm_14, + msm_mux_pwm_15, + msm_mux_pwm_16, + msm_mux_pwm_17, + msm_mux_pwm_18, + msm_mux_pwm_19, + msm_mux_pwm_2, + msm_mux_pwm_3, + msm_mux_pwm_4, + msm_mux_pwm_5, + msm_mux_pwm_6, + msm_mux_pwm_7, + msm_mux_pwm_8, + msm_mux_pwm_9, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se4_l0_mira, + msm_mux_qup0_se4_l0_mirb, + msm_mux_qup0_se4_l1_mira, + msm_mux_qup0_se4_l1_mirb, + msm_mux_qup0_se4_l2_mira, + msm_mux_qup0_se4_l2_mirb, + msm_mux_qup0_se4_l3_mira, + msm_mux_qup0_se4_l3_mirb, + msm_mux_qup0_se5, + msm_mux_qup0_se6, + msm_mux_qup1_se0, + msm_mux_qup1_se0_l3_mira, + msm_mux_qup1_se0_l3_mirb, + msm_mux_qup1_se1, + msm_mux_qup1_se1_l3_mira, + msm_mux_qup1_se1_l3_mirb, + msm_mux_qup1_se2, + msm_mux_qup1_se2_l3_mira, + msm_mux_qup1_se2_l3_mirb, + msm_mux_qup1_se3, + msm_mux_qup1_se3_l3_mira, + msm_mux_qup1_se3_l3_mirb, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se6_l0_mira, + msm_mux_qup1_se6_l0_mirb, + msm_mux_qup1_se6_l1_mira, + msm_mux_qup1_se6_l1_mirb, + msm_mux_sd_write_protect, + msm_mux_sdcc5_vdd2_on, + msm_mux_tb_trig_sdc2, + msm_mux_tgu_ch0_trigout, + msm_mux_tgu_ch1_trigout, + msm_mux_tgu_ch2_trigout, + msm_mux_tgu_ch3_trigout, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_usb0_phy_ps, + msm_mux_usb2phy_ac_en, + msm_mux_vsense_trigger_mirnat, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", "gpio210", "gpio211", "gpio212", + "gpio213", "gpio214", "gpio215", "gpio216", "gpio217", "gpio218", + "gpio219", "gpio220", "gpio221", "gpio222", "gpio223", +}; + +static const char *const atest_char_groups[] = { + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const atest_usb_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", +}; + +static const char *const audio_ext_mclk0_groups[] = { + "gpio162", +}; + +static const char *const audio_ext_mclk1_groups[] = { + "gpio116", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio162", +}; + +static const char *const cam_mclk_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const cci_async_in_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", + "gpio47", "gpio48", +}; + +static const char *const cci_i2c_scl_groups[] = { + "gpio1", "gpio3", "gpio5", "gpio7", "gpio9", "gpio11", "gpio13", + "gpio15", "gpio17", "gpio19", "gpio50", "gpio52", +}; + +static const char *const cci_i2c_sda_groups[] = { + "gpio0", "gpio2", "gpio4", "gpio6", "gpio8", "gpio10", "gpio12", + "gpio14", "gpio16", "gpio18", "gpio49", "gpio51", +}; + +static const char *const cci_timer_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", + "gpio39", "gpio45", "gpio46", "gpio47", "gpio49", "gpio50", "gpio51", + "gpio53", "gpio54", "gpio55", "gpio56", +}; + +static const char *const cmu_rng_groups[] = { + "gpio128", "gpio129", "gpio130", "gpio131", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio133", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio5", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio2", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio3", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio4", +}; + +static const char *const ddr_pxi0_groups[] = { + "gpio126", "gpio127", +}; + +static const char *const ddr_pxi1_groups[] = { + "gpio128", "gpio129", +}; + +static const char *const ddr_pxi2_groups[] = { + "gpio130", "gpio131", +}; + +static const char *const ddr_pxi3_groups[] = { + "gpio132", "gpio133", +}; + +static const char *const dp0_hot_groups[] = { + "gpio103", +}; + +static const char *const edp0_hot_groups[] = { + "gpio104", "gpio147", +}; + +static const char *const edp0_lcd_self_groups[] = { + "gpio106", +}; + +static const char *const edp1_dpu0_lcd_groups[] = { + "gpio107", +}; + +static const char *const edp1_dpu1_lcd_groups[] = { + "gpio107", +}; + +static const char *const edp1_hot_groups[] = { + "gpio105", "gpio148", +}; + +static const char *const gcc_gp1_groups[] = { + "gpio48", "gpio138", +}; + +static const char *const gcc_gp10_groups[] = { + "gpio108", +}; + +static const char *const gcc_gp11_groups[] = { + "gpio109", +}; + +static const char *const gcc_gp2_groups[] = { + "gpio53", "gpio139", +}; + +static const char *const gcc_gp3_groups[] = { + "gpio54", "gpio140", +}; + +static const char *const gcc_gp4_groups[] = { + "gpio62", +}; + +static const char *const gcc_gp5_groups[] = { + "gpio68", +}; + +static const char *const gcc_gp6_groups[] = { + "gpio74", +}; + +static const char *const gcc_gp7_groups[] = { + "gpio80", +}; + +static const char *const gcc_gp8_groups[] = { + "gpio87", +}; + +static const char *const gcc_gp9_groups[] = { + "gpio107", +}; + +static const char *const i2s0_data0_groups[] = { + "gpio163", +}; + +static const char *const i2s0_data1_groups[] = { + "gpio165", +}; + +static const char *const i2s0_sck_groups[] = { + "gpio164", +}; + +static const char *const i2s0_ws_groups[] = { + "gpio166", +}; + +static const char *const i2s2_data0_groups[] = { + "gpio155", +}; + +static const char *const i2s2_data1_groups[] = { + "gpio154", +}; + +static const char *const i2s2_sck_groups[] = { + "gpio156", +}; + +static const char *const i2s2_ws_groups[] = { + "gpio157", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio57", "gpio58", "gpio63", "gpio64", "gpio94", "gpio95", "gpio98", + "gpio99", +}; + +static const char *const jitter_bist_groups[] = { + "gpio158", +}; + +static const char *const mdp0_vsync_groups[] = { + "gpio110", "gpio111", "gpio150", "gpio151", +}; + +static const char *const mdp0_vsync0_out_groups[] = { + "gpio69", +}; + +static const char *const mdp0_vsync1_out_groups[] = { + "gpio70", +}; + +static const char *const mdp0_vsync2_out_groups[] = { + "gpio71", +}; + +static const char *const mdp0_vsync3_out_groups[] = { + "gpio72", +}; + +static const char *const mdp0_vsync4_out_groups[] = { + "gpio73", +}; + +static const char *const mdp0_vsync5_out_groups[] = { + "gpio74", +}; + +static const char *const mdp0_vsync6_out_groups[] = { + "gpio75", +}; + +static const char *const mdp0_vsync7_out_groups[] = { + "gpio76", +}; + +static const char *const mdp0_vsync8_out_groups[] = { + "gpio77", +}; + +static const char *const mdp1_vsync_groups[] = { + "gpio112", "gpio113", "gpio152", "gpio153", +}; + +static const char *const mdp1_vsync0_out_groups[] = { + "gpio60", +}; + +static const char *const mdp1_vsync1_out_groups[] = { + "gpio61", +}; + +static const char *const mdp1_vsync2_out_groups[] = { + "gpio62", +}; + +static const char *const mdp1_vsync3_out_groups[] = { + "gpio63", +}; + +static const char *const mdp1_vsync4_out_groups[] = { + "gpio64", +}; + +static const char *const mdp1_vsync5_out_groups[] = { + "gpio65", +}; + +static const char *const mdp1_vsync6_out_groups[] = { + "gpio66", +}; + +static const char *const mdp1_vsync7_out_groups[] = { + "gpio67", +}; + +static const char *const mdp1_vsync8_out_groups[] = { + "gpio68", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio118", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio142", +}; + +static const char *const pcie2_clk_req_n_groups[] = { + "gpio171", +}; + +static const char *const phase_flag_groups[] = { + "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", "gpio18", "gpio19", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio96", + "gpio97", "gpio100", "gpio101", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio157", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio159", +}; + +static const char *const prng_rosc0_groups[] = { + "gpio29", +}; + +static const char *const prng_rosc1_groups[] = { + "gpio30", +}; + +static const char *const prng_rosc2_groups[] = { + "gpio28", +}; + +static const char *const prng_rosc3_groups[] = { + "gpio27", +}; + +static const char *const pwm_0_groups[] = { + "gpio100", +}; + +static const char *const pwm_1_groups[] = { + "gpio101", +}; + +static const char *const pwm_10_groups[] = { + "gpio84", +}; + +static const char *const pwm_11_groups[] = { + "gpio108", +}; + +static const char *const pwm_12_groups[] = { + "gpio109", +}; + +static const char *const pwm_13_groups[] = { + "gpio19", +}; + +static const char *const pwm_14_groups[] = { + "gpio31", +}; + +static const char *const pwm_15_groups[] = { + "gpio52", +}; + +static const char *const pwm_16_groups[] = { + "gpio114", +}; + +static const char *const pwm_17_groups[] = { + "gpio149", +}; + +static const char *const pwm_18_groups[] = { + "gpio169", +}; + +static const char *const pwm_19_groups[] = { + "gpio173", +}; + +static const char *const pwm_2_groups[] = { + "gpio60", +}; + +static const char *const pwm_3_groups[] = { + "gpio61", +}; + +static const char *const pwm_4_groups[] = { + "gpio66", +}; + +static const char *const pwm_5_groups[] = { + "gpio67", +}; + +static const char *const pwm_6_groups[] = { + "gpio72", +}; + +static const char *const pwm_7_groups[] = { + "gpio73", +}; + +static const char *const pwm_8_groups[] = { + "gpio78", +}; + +static const char *const pwm_9_groups[] = { + "gpio79", +}; + +static const char *const qdss_cti_groups[] = { + "gpio42", "gpio43", "gpio114", "gpio115", "gpio154", "gpio155", + "gpio156", "gpio157", +}; + +static const char *const qdss_gpio_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49", "gpio134", "gpio135", "gpio191", + "gpio192", "gpio193", "gpio194", "gpio197", "gpio198", "gpio202", + "gpio203", "gpio206", "gpio207", "gpio215", "gpio216", "gpio217", + "gpio219", "gpio221", "gpio223", +}; + +static const char *const qup0_se0_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", +}; + +static const char *const qup0_se1_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char *const qup0_se2_groups[] = { + "gpio150", "gpio151", "gpio152", "gpio153", +}; + +static const char *const qup0_se3_groups[] = { + "gpio134", "gpio135", "gpio136", "gpio137", +}; + +static const char *const qup0_se4_groups[] = { + "gpio166", "gpio167", "gpio168", +}; + +static const char *const qup0_se4_l0_mira_groups[] = { + "gpio130", +}; + +static const char *const qup0_se4_l0_mirb_groups[] = { + "gpio162", +}; + +static const char *const qup0_se4_l1_mira_groups[] = { + "gpio131", +}; + +static const char *const qup0_se4_l1_mirb_groups[] = { + "gpio163", +}; + +static const char *const qup0_se4_l2_mira_groups[] = { + "gpio132", +}; + +static const char *const qup0_se4_l2_mirb_groups[] = { + "gpio164", +}; + +static const char *const qup0_se4_l3_mira_groups[] = { + "gpio133", +}; + +static const char *const qup0_se4_l3_mirb_groups[] = { + "gpio165", +}; + +static const char *const qup0_se5_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", +}; + +static const char *const qup0_se6_groups[] = { + "gpio156", "gpio157", "gpio158", "gpio159", +}; + +static const char *const qup1_se0_groups[] = { + "gpio57", "gpio58", "gpio59", +}; + +static const char *const qup1_se0_l3_mira_groups[] = { + "gpio60", +}; + +static const char *const qup1_se0_l3_mirb_groups[] = { + "gpio62", +}; + +static const char *const qup1_se1_groups[] = { + "gpio63", "gpio64", "gpio65", +}; + +static const char *const qup1_se1_l3_mira_groups[] = { + "gpio66", +}; + +static const char *const qup1_se1_l3_mirb_groups[] = { + "gpio68", +}; + +static const char *const qup1_se2_groups[] = { + "gpio69", "gpio70", "gpio71", +}; + +static const char *const qup1_se2_l3_mira_groups[] = { + "gpio72", +}; + +static const char *const qup1_se2_l3_mirb_groups[] = { + "gpio74", +}; + +static const char *const qup1_se3_groups[] = { + "gpio75", "gpio76", "gpio77", +}; + +static const char *const qup1_se3_l3_mira_groups[] = { + "gpio78", +}; + +static const char *const qup1_se3_l3_mirb_groups[] = { + "gpio80", +}; + +static const char *const qup1_se4_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", +}; + +static const char *const qup1_se5_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", +}; + +static const char *const qup1_se6_groups[] = { + "gpio105", "gpio106", +}; + +static const char *const qup1_se6_l0_mira_groups[] = { + "gpio92", +}; + +static const char *const qup1_se6_l0_mirb_groups[] = { + "gpio103", +}; + +static const char *const qup1_se6_l1_mira_groups[] = { + "gpio93", +}; + +static const char *const qup1_se6_l1_mirb_groups[] = { + "gpio104", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio155", +}; + +static const char *const sdcc5_vdd2_on_groups[] = { + "gpio154", +}; + +static const char *const tb_trig_sdc2_groups[] = { + "gpio174", +}; + +static const char *const tgu_ch0_trigout_groups[] = { + "gpio163", +}; + +static const char *const tgu_ch1_trigout_groups[] = { + "gpio164", +}; + +static const char *const tgu_ch2_trigout_groups[] = { + "gpio165", +}; + +static const char *const tgu_ch3_trigout_groups[] = { + "gpio166", +}; + +static const char *const tmess_prng0_groups[] = { + "gpio26", +}; + +static const char *const tmess_prng1_groups[] = { + "gpio25", +}; + +static const char *const tmess_prng2_groups[] = { + "gpio24", +}; + +static const char *const tmess_prng3_groups[] = { + "gpio23", +}; + +static const char *const tsense_pwm1_groups[] = { + "gpio102", +}; + +static const char *const tsense_pwm2_groups[] = { + "gpio102", +}; + +static const char *const usb0_phy_ps_groups[] = { + "gpio160", +}; + +static const char *const usb2phy_ac_en_groups[] = { + "gpio141", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio126", +}; + +static const struct pinfunction halliday_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk0), + MSM_PIN_FUNCTION(audio_ext_mclk1), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(cmu_rng), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp0_hot), + MSM_PIN_FUNCTION(edp0_hot), + MSM_PIN_FUNCTION(edp0_lcd_self), + MSM_PIN_FUNCTION(edp1_dpu0_lcd), + MSM_PIN_FUNCTION(edp1_dpu1_lcd), + MSM_PIN_FUNCTION(edp1_hot), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp10), + MSM_PIN_FUNCTION(gcc_gp11), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gcc_gp4), + MSM_PIN_FUNCTION(gcc_gp5), + MSM_PIN_FUNCTION(gcc_gp6), + MSM_PIN_FUNCTION(gcc_gp7), + MSM_PIN_FUNCTION(gcc_gp8), + MSM_PIN_FUNCTION(gcc_gp9), + MSM_PIN_FUNCTION(i2s0_data0), + MSM_PIN_FUNCTION(i2s0_data1), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(i2s2_data0), + MSM_PIN_FUNCTION(i2s2_data1), + MSM_PIN_FUNCTION(i2s2_sck), + MSM_PIN_FUNCTION(i2s2_ws), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp0_vsync), + MSM_PIN_FUNCTION(mdp0_vsync0_out), + MSM_PIN_FUNCTION(mdp0_vsync1_out), + MSM_PIN_FUNCTION(mdp0_vsync2_out), + MSM_PIN_FUNCTION(mdp0_vsync3_out), + MSM_PIN_FUNCTION(mdp0_vsync4_out), + MSM_PIN_FUNCTION(mdp0_vsync5_out), + MSM_PIN_FUNCTION(mdp0_vsync6_out), + MSM_PIN_FUNCTION(mdp0_vsync7_out), + MSM_PIN_FUNCTION(mdp0_vsync8_out), + MSM_PIN_FUNCTION(mdp1_vsync), + MSM_PIN_FUNCTION(mdp1_vsync0_out), + MSM_PIN_FUNCTION(mdp1_vsync1_out), + MSM_PIN_FUNCTION(mdp1_vsync2_out), + MSM_PIN_FUNCTION(mdp1_vsync3_out), + MSM_PIN_FUNCTION(mdp1_vsync4_out), + MSM_PIN_FUNCTION(mdp1_vsync5_out), + MSM_PIN_FUNCTION(mdp1_vsync6_out), + MSM_PIN_FUNCTION(mdp1_vsync7_out), + MSM_PIN_FUNCTION(mdp1_vsync8_out), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie2_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(pwm_0), + MSM_PIN_FUNCTION(pwm_1), + MSM_PIN_FUNCTION(pwm_10), + MSM_PIN_FUNCTION(pwm_11), + MSM_PIN_FUNCTION(pwm_12), + MSM_PIN_FUNCTION(pwm_13), + MSM_PIN_FUNCTION(pwm_14), + MSM_PIN_FUNCTION(pwm_15), + MSM_PIN_FUNCTION(pwm_16), + MSM_PIN_FUNCTION(pwm_17), + MSM_PIN_FUNCTION(pwm_18), + MSM_PIN_FUNCTION(pwm_19), + MSM_PIN_FUNCTION(pwm_2), + MSM_PIN_FUNCTION(pwm_3), + MSM_PIN_FUNCTION(pwm_4), + MSM_PIN_FUNCTION(pwm_5), + MSM_PIN_FUNCTION(pwm_6), + MSM_PIN_FUNCTION(pwm_7), + MSM_PIN_FUNCTION(pwm_8), + MSM_PIN_FUNCTION(pwm_9), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se4_l0_mira), + MSM_PIN_FUNCTION(qup0_se4_l0_mirb), + MSM_PIN_FUNCTION(qup0_se4_l1_mira), + MSM_PIN_FUNCTION(qup0_se4_l1_mirb), + MSM_PIN_FUNCTION(qup0_se4_l2_mira), + MSM_PIN_FUNCTION(qup0_se4_l2_mirb), + MSM_PIN_FUNCTION(qup0_se4_l3_mira), + MSM_PIN_FUNCTION(qup0_se4_l3_mirb), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup0_se6), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se0_l3_mira), + MSM_PIN_FUNCTION(qup1_se0_l3_mirb), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se1_l3_mira), + MSM_PIN_FUNCTION(qup1_se1_l3_mirb), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se2_l3_mira), + MSM_PIN_FUNCTION(qup1_se2_l3_mirb), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se3_l3_mira), + MSM_PIN_FUNCTION(qup1_se3_l3_mirb), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se6_l0_mira), + MSM_PIN_FUNCTION(qup1_se6_l0_mirb), + MSM_PIN_FUNCTION(qup1_se6_l1_mira), + MSM_PIN_FUNCTION(qup1_se6_l1_mirb), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdcc5_vdd2_on), + MSM_PIN_FUNCTION(tb_trig_sdc2), + MSM_PIN_FUNCTION(tgu_ch0_trigout), + MSM_PIN_FUNCTION(tgu_ch1_trigout), + MSM_PIN_FUNCTION(tgu_ch2_trigout), + MSM_PIN_FUNCTION(tgu_ch3_trigout), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(usb2phy_ac_en), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup halliday_groups[] = { + [0] = PINGROUP(0, cci_i2c_sda, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, cci_i2c_scl, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, cci_i2c_sda, ddr_bist_fail, _, phase_flag, _, _, _, _, _), + [3] = PINGROUP(3, cci_i2c_scl, ddr_bist_start, _, phase_flag, _, _, _, _, _), + [4] = PINGROUP(4, cci_i2c_sda, ddr_bist_stop, _, phase_flag, _, _, _, _, _), + [5] = PINGROUP(5, cci_i2c_scl, ddr_bist_complete, _, phase_flag, _, _, _, _, _), + [6] = PINGROUP(6, cci_i2c_sda, _, phase_flag, _, _, _, _, _, _), + [7] = PINGROUP(7, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _), + [8] = PINGROUP(8, cci_i2c_sda, _, phase_flag, _, _, _, _, _, _), + [9] = PINGROUP(9, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _), + [10] = PINGROUP(10, cci_i2c_sda, _, phase_flag, _, _, _, _, _, _), + [11] = PINGROUP(11, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _), + [12] = PINGROUP(12, cci_i2c_sda, _, phase_flag, _, _, _, _, _, _), + [13] = PINGROUP(13, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _), + [14] = PINGROUP(14, cci_i2c_sda, _, phase_flag, _, _, _, _, _, _), + [15] = PINGROUP(15, cci_i2c_scl, _, phase_flag, atest_char, _, _, _, _, _), + [16] = PINGROUP(16, cci_i2c_sda, _, phase_flag, atest_char, _, _, _, _, _), + [17] = PINGROUP(17, cci_i2c_scl, _, phase_flag, atest_char, _, _, _, _, _), + [18] = PINGROUP(18, cci_i2c_sda, _, phase_flag, atest_char, _, _, _, _, _), + [19] = PINGROUP(19, cci_i2c_scl, pwm_13, _, phase_flag, atest_char, _, _, _, _), + [20] = PINGROUP(20, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [21] = PINGROUP(21, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [22] = PINGROUP(22, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [23] = PINGROUP(23, cam_mclk, tmess_prng3, qdss_gpio, _, _, _, _, _, _), + [24] = PINGROUP(24, cam_mclk, tmess_prng2, qdss_gpio, _, _, _, _, _, _), + [25] = PINGROUP(25, cam_mclk, tmess_prng1, qdss_gpio, _, _, _, _, _, _), + [26] = PINGROUP(26, cam_mclk, tmess_prng0, qdss_gpio, _, _, _, _, _, _), + [27] = PINGROUP(27, cam_mclk, prng_rosc3, qdss_gpio, _, _, _, _, _, _), + [28] = PINGROUP(28, cam_mclk, prng_rosc2, qdss_gpio, _, _, _, _, _, _), + [29] = PINGROUP(29, cam_mclk, prng_rosc0, qdss_gpio, _, _, _, _, _, _), + [30] = PINGROUP(30, cam_mclk, prng_rosc1, qdss_gpio, _, _, _, _, _, _), + [31] = PINGROUP(31, cam_mclk, pwm_14, qdss_gpio, _, _, _, _, _, _), + [32] = PINGROUP(32, cci_timer, _, phase_flag, _, _, _, _, _, _), + [33] = PINGROUP(33, cci_timer, _, phase_flag, _, _, _, _, _, _), + [34] = PINGROUP(34, cci_timer, _, phase_flag, _, _, _, _, _, _), + [35] = PINGROUP(35, cci_timer, _, _, phase_flag, _, _, _, _, _), + [36] = PINGROUP(36, cci_timer, _, _, phase_flag, _, _, _, _, _), + [37] = PINGROUP(37, cci_timer, _, _, phase_flag, _, _, _, _, _), + [38] = PINGROUP(38, cci_timer, _, phase_flag, _, _, _, _, _, _), + [39] = PINGROUP(39, cci_timer, _, phase_flag, _, _, _, _, _, _), + [40] = PINGROUP(40, cci_async_in, _, phase_flag, _, _, _, _, _, _), + [41] = PINGROUP(41, cci_async_in, _, phase_flag, _, _, _, _, _, _), + [42] = PINGROUP(42, cci_async_in, qdss_cti, _, _, _, _, _, _, _), + [43] = PINGROUP(43, cci_async_in, qdss_cti, _, _, _, _, _, _, _), + [44] = PINGROUP(44, cci_async_in, qdss_gpio, _, _, _, _, _, _, _), + [45] = PINGROUP(45, cci_async_in, cci_timer, qdss_gpio, _, _, _, _, _, _), + [46] = PINGROUP(46, cci_async_in, cci_timer, qdss_gpio, _, _, _, _, _, _), + [47] = PINGROUP(47, cci_async_in, cci_timer, qdss_gpio, _, _, _, _, _, _), + [48] = PINGROUP(48, cci_async_in, gcc_gp1, qdss_gpio, _, _, _, _, _, _), + [49] = PINGROUP(49, cci_i2c_sda, cci_timer, qdss_gpio, _, _, _, _, _, _), + [50] = PINGROUP(50, cci_i2c_scl, cci_timer, _, _, _, _, _, _, _), + [51] = PINGROUP(51, cci_i2c_sda, cci_timer, _, _, _, _, _, _, _), + [52] = PINGROUP(52, cci_i2c_scl, pwm_15, _, _, _, _, _, _, _), + [53] = PINGROUP(53, cci_timer, gcc_gp2, _, _, _, _, _, _, _), + [54] = PINGROUP(54, cci_timer, gcc_gp3, _, _, _, _, _, _, _), + [55] = PINGROUP(55, cci_timer, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, cci_timer, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup1_se0, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup1_se0_l3_mira, pwm_2, mdp1_vsync0_out, _, _, _, _, _, _), + [61] = PINGROUP(61, pwm_3, mdp1_vsync1_out, _, _, _, _, _, _, _), + [62] = PINGROUP(62, gcc_gp4, qup1_se0_l3_mirb, mdp1_vsync2_out, _, _, _, _, _, _), + [63] = PINGROUP(63, qup1_se1, ibi_i3c, mdp1_vsync3_out, _, _, _, _, _, _), + [64] = PINGROUP(64, qup1_se1, ibi_i3c, mdp1_vsync4_out, _, _, _, _, _, _), + [65] = PINGROUP(65, qup1_se1, mdp1_vsync5_out, _, _, _, _, _, _, _), + [66] = PINGROUP(66, qup1_se1_l3_mira, pwm_4, mdp1_vsync6_out, _, _, _, _, _, _), + [67] = PINGROUP(67, pwm_5, mdp1_vsync7_out, _, _, _, _, _, _, _), + [68] = PINGROUP(68, gcc_gp5, qup1_se1_l3_mirb, mdp1_vsync8_out, _, _, _, _, _, _), + [69] = PINGROUP(69, qup1_se2, mdp0_vsync0_out, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qup1_se2, mdp0_vsync1_out, _, _, _, _, _, _, _), + [71] = PINGROUP(71, qup1_se2, mdp0_vsync2_out, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qup1_se2_l3_mira, pwm_6, mdp0_vsync3_out, _, _, _, _, _, _), + [73] = PINGROUP(73, pwm_7, mdp0_vsync4_out, _, _, _, _, _, _, _), + [74] = PINGROUP(74, gcc_gp6, qup1_se2_l3_mirb, mdp0_vsync5_out, _, _, _, _, _, _), + [75] = PINGROUP(75, qup1_se3, mdp0_vsync6_out, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qup1_se3, mdp0_vsync7_out, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qup1_se3, mdp0_vsync8_out, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qup1_se3_l3_mira, pwm_8, _, _, _, _, _, _, _), + [79] = PINGROUP(79, pwm_9, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, gcc_gp7, qup1_se3_l3_mirb, _, _, _, _, _, _, _), + [81] = PINGROUP(81, qup1_se4, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, qup1_se4, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, qup1_se4, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, qup1_se4, pwm_10, _, _, _, _, _, _, _), + [85] = PINGROUP(85, qup1_se4, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, qup1_se4, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, gcc_gp8, qup1_se4, _, _, _, _, _, _, _), + [88] = PINGROUP(88, qup1_se5, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, qup1_se5, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, qup1_se5, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, qup1_se5, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, qup1_se6_l0_mira, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, qup1_se6_l1_mira, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, qup0_se0, ibi_i3c, _, _, _, _, _, _, _), + [95] = PINGROUP(95, qup0_se0, ibi_i3c, _, _, _, _, _, _, _), + [96] = PINGROUP(96, qup0_se0, _, phase_flag, _, _, _, _, _, _), + [97] = PINGROUP(97, qup0_se0, _, phase_flag, _, _, _, _, _, _), + [98] = PINGROUP(98, qup0_se1, ibi_i3c, _, _, _, _, _, _, _), + [99] = PINGROUP(99, qup0_se1, ibi_i3c, _, _, _, _, _, _, _), + [100] = PINGROUP(100, qup0_se1, pwm_0, _, phase_flag, _, _, _, _, _), + [101] = PINGROUP(101, qup0_se1, pwm_1, _, phase_flag, _, _, _, _, _), + [102] = PINGROUP(102, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _, _), + [103] = PINGROUP(103, qup1_se6_l0_mirb, dp0_hot, _, _, _, _, _, _, _), + [104] = PINGROUP(104, qup1_se6_l1_mirb, edp0_hot, _, _, _, _, _, _, _), + [105] = PINGROUP(105, qup1_se6, edp1_hot, _, _, _, _, _, _, _), + [106] = PINGROUP(106, qup1_se6, edp0_lcd_self, _, _, _, _, _, _, _), + [107] = PINGROUP(107, gcc_gp9, edp1_dpu1_lcd, edp1_dpu0_lcd, _, _, _, _, _, _), + [108] = PINGROUP(108, gcc_gp10, pwm_11, _, _, _, _, _, _, _), + [109] = PINGROUP(109, gcc_gp11, pwm_12, _, _, _, _, _, _, _), + [110] = PINGROUP(110, mdp0_vsync, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, mdp0_vsync, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, mdp1_vsync, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, mdp1_vsync, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, pwm_16, qdss_cti, _, _, _, _, _, _, _), + [115] = PINGROUP(115, qdss_cti, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, audio_ext_mclk1, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, pcie0_clk_req_n, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, qup0_se5, _, vsense_trigger_mirnat, atest_usb, ddr_pxi0, _, _, _, _), + [127] = PINGROUP(127, qup0_se5, _, atest_usb, ddr_pxi0, _, _, _, _, _), + [128] = PINGROUP(128, qup0_se5, cmu_rng, _, atest_usb, ddr_pxi1, _, _, _, _), + [129] = PINGROUP(129, qup0_se5, cmu_rng, _, atest_usb, ddr_pxi1, _, _, _, _), + [130] = PINGROUP(130, qup0_se4_l0_mira, cmu_rng, _, atest_usb, ddr_pxi2, _, _, _, _), + [131] = PINGROUP(131, qup0_se4_l1_mira, cmu_rng, _, _, ddr_pxi2, _, _, _, _), + [132] = PINGROUP(132, qup0_se4_l2_mira, _, _, ddr_pxi3, _, _, _, _, _), + [133] = PINGROUP(133, qup0_se4_l3_mira, dbg_out_clk, ddr_pxi3, _, _, _, _, _, _), + [134] = PINGROUP(134, qup0_se3, qdss_gpio, _, _, _, _, _, _, _), + [135] = PINGROUP(135, qup0_se3, qdss_gpio, _, _, _, _, _, _, _), + [136] = PINGROUP(136, qup0_se3, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, qup0_se3, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, gcc_gp1, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, gcc_gp2, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, gcc_gp3, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, usb2phy_ac_en, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, pcie1_clk_req_n, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, edp0_hot, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, edp1_hot, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, pwm_17, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, qup0_se2, mdp0_vsync, _, _, _, _, _, _, _), + [151] = PINGROUP(151, qup0_se2, mdp0_vsync, _, _, _, _, _, _, _), + [152] = PINGROUP(152, qup0_se2, mdp1_vsync, _, _, _, _, _, _, _), + [153] = PINGROUP(153, qup0_se2, mdp1_vsync, _, _, _, _, _, _, _), + [154] = PINGROUP(154, i2s2_data1, sdcc5_vdd2_on, _, qdss_cti, _, _, _, _, _), + [155] = PINGROUP(155, i2s2_data0, sd_write_protect, qdss_cti, _, _, _, _, _, _), + [156] = PINGROUP(156, i2s2_sck, qup0_se6, _, qdss_cti, _, _, _, _, _), + [157] = PINGROUP(157, i2s2_ws, qup0_se6, pll_bist_sync, qdss_cti, _, _, _, _, _), + [158] = PINGROUP(158, qup0_se6, jitter_bist, _, _, _, _, _, _, _), + [159] = PINGROUP(159, qup0_se6, pll_clk_aux, _, _, _, _, _, _, _), + [160] = PINGROUP(160, usb0_phy_ps, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qup0_se4_l0_mirb, audio_ext_mclk0, audio_ref_clk, _, _, _, _, _, _), + [163] = PINGROUP(163, qup0_se4_l1_mirb, i2s0_data0, tgu_ch0_trigout, _, _, _, _, _, _), + [164] = PINGROUP(164, qup0_se4_l2_mirb, i2s0_sck, tgu_ch1_trigout, _, _, _, _, _, _), + [165] = PINGROUP(165, qup0_se4_l3_mirb, i2s0_data1, tgu_ch2_trigout, _, _, _, _, _, _), + [166] = PINGROUP(166, qup0_se4, i2s0_ws, tgu_ch3_trigout, _, _, _, _, _, _), + [167] = PINGROUP(167, qup0_se4, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, qup0_se4, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, pwm_18, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, pcie2_clk_req_n, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, pwm_19, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, tb_trig_sdc2, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), + [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _), + [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _), + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _), + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _), + [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _), + [192] = PINGROUP(192, qdss_gpio, _, _, _, _, _, _, _, _), + [193] = PINGROUP(193, qdss_gpio, _, _, _, _, _, _, _, _), + [194] = PINGROUP(194, qdss_gpio, _, _, _, _, _, _, _, _), + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _), + [196] = PINGROUP(196, _, _, _, _, _, _, _, _, _), + [197] = PINGROUP(197, qdss_gpio, _, _, _, _, _, _, _, _), + [198] = PINGROUP(198, qdss_gpio, _, _, _, _, _, _, _, _), + [199] = PINGROUP(199, _, _, _, _, _, _, _, _, _), + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _), + [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _), + [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _), + [204] = PINGROUP(204, _, _, _, _, _, _, _, _, _), + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _), + [206] = PINGROUP(206, qdss_gpio, _, _, _, _, _, _, _, _), + [207] = PINGROUP(207, qdss_gpio, _, _, _, _, _, _, _, _), + [208] = PINGROUP(208, _, _, _, _, _, _, _, _, _), + [209] = PINGROUP(209, _, _, _, _, _, _, _, _, _), + [210] = PINGROUP(210, _, _, _, _, _, _, _, _, _), + [211] = PINGROUP(211, _, _, _, _, _, _, _, _, _), + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _), + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _), + [214] = PINGROUP(214, _, _, _, _, _, _, _, _, _), + [215] = PINGROUP(215, qdss_gpio, _, _, _, _, _, _, _, _), + [216] = PINGROUP(216, qdss_gpio, _, _, _, _, _, _, _, _), + [217] = PINGROUP(217, qdss_gpio, _, _, _, _, _, _, _, _), + [218] = PINGROUP(218, _, _, _, _, _, _, _, _, _), + [219] = PINGROUP(219, qdss_gpio, _, _, _, _, _, _, _, _), + [220] = PINGROUP(220, _, _, _, _, _, _, _, _, _), + [221] = PINGROUP(221, qdss_gpio, _, _, _, _, _, _, _, _), + [222] = PINGROUP(222, _, _, _, _, _, _, _, _, _), + [223] = PINGROUP(223, qdss_gpio, _, _, _, _, _, _, _, _), + [224] = UFS_RESET(ufs_reset, 0xee000), + [225] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe4000, 14, 6), + [226] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe4000, 11, 3), + [227] = SDC_QDSD_PINGROUP(sdc2_data, 0xe4000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map halliday_pdc_map[] = { + { 18, 99 }, { 31, 120 }, { 37, 101 }, { 40, 103 }, { 41, 104 }, + { 43, 106 }, { 44, 107 }, { 45, 92 }, { 46, 83 }, { 47, 86 }, + { 53, 111 }, { 57, 121 }, { 60, 56 }, { 61, 108 }, { 62, 109 }, + { 66, 110 }, { 68, 57 }, { 72, 112 }, { 74, 43 }, { 78, 114 }, + { 84, 67 }, { 86, 66 }, { 87, 100 }, { 91, 102 }, { 94, 93 }, + { 98, 123 }, { 100, 44 }, { 101, 97 }, { 103, 75 }, { 104, 52 }, + { 106, 48 }, { 110, 53 }, { 111, 76 }, { 112, 49 }, { 113, 50 }, + { 115, 54 }, { 118, 58 }, { 119, 77 }, { 122, 62 }, { 123, 63 }, + { 129, 61 }, { 133, 65 }, { 137, 69 }, { 139, 70 }, { 142, 71 }, + { 145, 74 }, { 146, 45 }, { 147, 78 }, { 148, 60 }, { 150, 119 }, + { 152, 85 }, { 153, 79 }, { 154, 80 }, { 155, 81 }, { 157, 84 }, + { 163, 88 }, { 164, 89 }, { 165, 73 }, { 166, 90 }, { 167, 91 }, + { 169, 82 }, { 170, 95 }, { 171, 98 }, { 172, 47 }, { 175, 46 }, + { 186, 129 }, { 189, 131 }, { 194, 116 }, { 196, 117 }, { 199, 113 }, + { 201, 128 }, { 207, 115 }, { 208, 132 }, { 210, 135 }, { 212, 136 }, + { 215, 137 }, +}; + +static const struct msm_pinctrl_soc_data halliday_tlmm = { + .pins = halliday_pins, + .npins = ARRAY_SIZE(halliday_pins), + .functions = halliday_functions, + .nfunctions = ARRAY_SIZE(halliday_functions), + .groups = halliday_groups, + .ngroups = ARRAY_SIZE(halliday_groups), + .ngpios = 225, + .wakeirq_map = halliday_pdc_map, + .nwakeirq_map = ARRAY_SIZE(halliday_pdc_map), + .egpio_func = 9, +}; + +static int halliday_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &halliday_tlmm); +} + +static const struct of_device_id halliday_tlmm_of_match[] = { + { .compatible = "qcom,halliday-tlmm", }, + {}, +}; +MODULE_DEVICE_TABLE(of, halliday_tlmm_of_match); + +static struct platform_driver halliday_tlmm_driver = { + .driver = { + .name = "halliday-tlmm", + .of_match_table = halliday_tlmm_of_match, + }, + .probe = halliday_tlmm_probe, +}; + +static int __init halliday_tlmm_init(void) +{ + return platform_driver_register(&halliday_tlmm_driver); +} +arch_initcall(halliday_tlmm_init); + +static void __exit halliday_tlmm_exit(void) +{ + platform_driver_unregister(&halliday_tlmm_driver); +} +module_exit(halliday_tlmm_exit); + +MODULE_DESCRIPTION("QTI Halliday TLMM driver"); +MODULE_LICENSE("GPL"); -- 2.55.0