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Mon, 09 Nov 2026 07:50:12 -0800 (PST) Received: from hu-naala-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b375604109sm17671616c88.10.2026.11.09.07.50.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 07:50:11 -0800 (PST) From: Nabige Aala Date: Mon, 09 Nov 2026 21:20:00 +0530 Subject: [PATCH] arm64: dts: qcom: mahua-crd: Enable DisplayPort X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261109-mahua-dp-v1-1-c1fdfb8eedb5@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAKfr8WoC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzNDQwMT3dzEjNJE3ZQC3ZQ0I1MTQwtjc0MjcyWg8oKi1LTMCrBR0bEQfnF pUlZqcglIv1JtLQD8k6LhbAAAAA== X-Change-ID: 20261104-mahua-dp-df2541837127 To: Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nabige Aala X-Mailer: b4 0.16-dev-d5d98 X-Developer-Signature: v=1; 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Enable the two DisplayPort controllers associated with the Type-C ports and define the supported link frequencies for their outputs. Signed-off-by: Nabige Aala --- This patch enables the DisplayPort support in Mahua CRD. Functional operation depends on following PHY PLL series: https://lore.kernel.org/all/20261001-glymur-phy-v3-v5-0-3848c2615d5a@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/mahua-crd.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts index 17e40f2a6259..2605c0e70c88 100644 --- a/arch/arm64/boot/dts/qcom/mahua-crd.dts +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -20,6 +20,22 @@ / { compatible = "qcom,mahua-crd", "qcom,mahua"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &pcie3b_phy { vdda-phy-supply = <&vreg_l3c_e1_0p89>; vdda-pll-supply = <&vreg_l2c_e1_1p14>; --- base-commit: d6bcfc94eb4da6e089c5473970cd96727292fd97 change-id: 20261104-mahua-dp-df2541837127 Best regards, -- Nabige Aala