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Mon, 09 Nov 2026 17:47:01 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:8bc4:8aec:108d:7a04]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-67c589c6f24sm692080d50.12.2026.11.09.17.47.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 17:47:01 -0800 (PST) From: Matt Turner Subject: [PATCH 0/8] powerpc/perf: mpc7450: Event fixes, SIAR sampling and sysfs event names Date: Mon, 09 Nov 2026 20:46:59 -0500 Message-Id: <20261109-ppc32-perf-v1-0-a6e8a55b3b48@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/x3MMQqAMAxA0atIZgMmioNXEYfapppFQwoiiHe3O L7h/weKuEqBqXnA5dKi51FBbQNxD8cmqKkauOORqBvRLPaMJp5xzYF6DjRwWqEG5pL1/mfz8r4 fI+XZ9FwAAAA= X-Change-ID: 20261106-ppc32-perf-bfa132a142db To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , "Ritesh Harjani (IBM)" , Shrikanth Hegde , Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1783; i=mattst88@gmail.com; h=from:subject:message-id; bh=+7BXvgmmUAJktVVUTJnPsJZ3PxH3Hy9JzygYzXxr5Gs=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLI+lU/2/FN3Z1FD/i6VJ15HRA/MWhaswvJpz8Wd2az/L Fknr5rv3PGRhUGMi2GmmCJL3HpFllltO5b6nJb+BTOHlQlkiLRIAwMQsDDw5SbmlRrpGOmZahvq GQIZOkbxEDk9Bo3M4uLS1CLdtIIih7z8ksSSzPy8Yr38gtS8gvQCvbTMtJKMjPyi4lSgEXp5qSW mro5uRoYGJpaOFmZOFo6mJs7OToZObo6Ozq5ORpbmJgbOlo4mrpbmDFycAjDXzLjE8E+l8fUT64 syu28nLq8Qmb3l6V+LqX8KlDZNeuWkc1OtyoeH4X/0mgm9vXd8v555yX/29fy5/hbb9umZJ5WG+ QUIeFVf2scLAA== X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A Patches 1-3 fix the MPC7450 perf driver's event tables against the manual (MPC7450UM Rev. 5, chapter 11). The worst is patch 3: an alternatives row joins three different events, so perf can report the count of a different event. In one test it was 374 times the real count. Patch 4 fills in the L1 data cache events, patch 5 adds the PMC6 copies of five L3 events to the alternatives table, and patch 6 adds a format/ directory. Patch 7 takes sample addresses from SIAR on 32-bit. When a counter overflows with interrupts disabled, the interrupted PC is where they are re-enabled; SIAR is not. Patch 8 names the events in sysfs. Tested on an iMac G4 (MPC7448). The 7448 has no L3, so patch 5 and the L3 half of patch 8 are untested. Signed-off-by: Matt Turner --- Matt Turner (8): powerpc/perf: mpc7450: Event 0x30d does not use the threshold powerpc/perf: mpc7450: Event 0x634 counts L2 prefetches, not L1I powerpc/perf: mpc7450: Remove the snoop retry alternatives powerpc/perf: mpc7450: Fill in the L1 data cache events powerpc/perf: mpc7450: Add the PMC6 L3 events to the alternatives table powerpc/perf: mpc7450: Export the event format in sysfs powerpc/perf: Use SIAR for sample addresses on 32-bit powerpc/perf: mpc7450: Export event names in sysfs arch/powerpc/perf/core-book3s.c | 55 ++++--- arch/powerpc/perf/mpc7450-events-list.h | 250 ++++++++++++++++++++++++++++++++ arch/powerpc/perf/mpc7450-pmu.c | 118 +++++++++++++-- 3 files changed, 388 insertions(+), 35 deletions(-) --- base-commit: d68ce4e71248e1ff5af9654b407541d9260b3ba5 change-id: 20261106-ppc32-perf-bfa132a142db Best regards, -- Matt Turner