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Mon, 09 Nov 2026 17:47:04 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:8bc4:8aec:108d:7a04]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8b39324bf84sm8634687b3.3.2026.11.09.17.47.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 17:47:04 -0800 (PST) From: Matt Turner Date: Mon, 09 Nov 2026 20:47:01 -0500 Subject: [PATCH 2/8] powerpc/perf: mpc7450: Event 0x634 counts L2 prefetches, not L1I X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261109-ppc32-perf-v1-2-a6e8a55b3b48@gmail.com> References: <20261109-ppc32-perf-v1-0-a6e8a55b3b48@gmail.com> In-Reply-To: <20261109-ppc32-perf-v1-0-a6e8a55b3b48@gmail.com> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , "Ritesh Harjani (IBM)" , Shrikanth Hegde , Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1849; i=mattst88@gmail.com; h=from:subject:message-id; bh=TwlNAcp6eC0hJG+v2/kOLi3vElXUnRdKI+S9gxs5PKI=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLI+lU9hd/Dtkpw88Tpj9D6m3TdNn3lZyG9ZnGfVtbhEd NltLrv2jo8sDGJcDDPFFFni1iuyzGrbsdTntPQvmDmsTCBDpEUaGICAhYEvNzGv1EjHSM9U21DP EMjQMYqHyOkxaGQWF5emFummFRQ55OWXJJZk5ucV6+UXpOYVpBfopWWmlWRk5BcVpwKN0MtLLTF 1dXQzMjQwsXS0MHOycDQ1cXZ2MnRyc3R0dnUysjQ3MXC2dDRxtTRn4OIUgLnmUy8jw/2q6LwdX6 5efnRlk4O3xGPtqVsrPrHWuEl2hD5S2tv8JIKRoX29p9NxxRpT/ZpITvnZE8vuPGjgivl1YNdUh yRnra2TOAE= X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A The cache event table maps L1-icache-prefetches to 0x634, PMC6 select 52. The manual (MPC7450UM Rev. 5, Table 11-14) calls that event "Prefetch engine request" and says it "counts new prefetches allocated in the prefetch unit". It is the first of six events about the L2 prefetch engine (selects 52-57), and the MPC7450 has no instruction cache prefetch event. On a 7448, a pointer chase over 64-byte nodes counts r634 at 0.00 per load when the working set fits in the 1 MB L2, and at 1.00 per load, one per L2 demand miss, at 4 MB. The engine starts a prefetch only when an access misses in every cache, fetches from the bus, and also fills the L3 if there is one (section 3.6.3.2), so it is a last-level prefetch with or without an L3. Report it as LL-prefetches, and L1-icache-prefetches as not supported. Fixes: 7325927e5a20 ("perf_counter: powerpc: Add processor back-end for MPC7450 family") Signed-off-by: Matt Turner --- arch/powerpc/perf/mpc7450-pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c index 564f6dac3a00..5a882d934645 100644 --- a/arch/powerpc/perf/mpc7450-pmu.c +++ b/arch/powerpc/perf/mpc7450-pmu.c @@ -370,12 +370,12 @@ static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { 0x129, 0x115 }, [C(OP_WRITE)] = { -1, -1 }, - [C(OP_PREFETCH)] = { 0x634, 0 }, + [C(OP_PREFETCH)] = { 0, 0 }, }, [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { 0, 0 }, [C(OP_WRITE)] = { 0, 0 }, - [C(OP_PREFETCH)] = { 0, 0 }, + [C(OP_PREFETCH)] = { 0x634, 0 }, }, [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { 0, 0x312 }, -- 2.55.0