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Mon, 09 Nov 2026 17:47:11 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:8bc4:8aec:108d:7a04]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8b393408893sm8423327b3.26.2026.11.09.17.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 17:47:08 -0800 (PST) From: Matt Turner Date: Mon, 09 Nov 2026 20:47:03 -0500 Subject: [PATCH 4/8] powerpc/perf: mpc7450: Fill in the L1 data cache events X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261109-ppc32-perf-v1-4-a6e8a55b3b48@gmail.com> References: <20261109-ppc32-perf-v1-0-a6e8a55b3b48@gmail.com> In-Reply-To: <20261109-ppc32-perf-v1-0-a6e8a55b3b48@gmail.com> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , "Ritesh Harjani (IBM)" , Shrikanth Hegde , Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1724; i=mattst88@gmail.com; h=from:subject:message-id; bh=vxh969Hcy9WrgNGikVvry8J80j4iE34/QdKKb/UQT9A=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLI+lU8xOlEfF3rij4y+FmuL7owp62wag77+brff8IKlV fPqKuM7HR9ZGMS4GGaKKbLErVdkmdW2Y6nPaelfMHNYmUCGSIs0MAABCwNfbmJeqZGOkZ6ptqGe IZChYxQPkdNj0MgsLi5NLdJNKyhyyMsvSSzJzM8r1ssvSM0rSC/QS8tMK8nIyC8qTgUaoZeXWmL q6uhmZGhgYuloYeZk4Whq4uzsZOjk5ujo7OpkZGluYuBs6WjiamnOwMUpAHONRDvDX9nqbTbqlZ K2J19eNft0e7U7+/sXCcYvPx+8snCVTzlzlwrD/0C5jjkX4ralP/lyILH4hD9bqfdlH7dLMyUmN 3dNNnp8iw8A X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A The L1D row of the cache event table has load and store misses but no accesses, and nothing for prefetches, so L1-dcache-loads, L1-dcache-stores and L1-dcache-prefetch-misses are not supported. The MPC7450 has no L1 data cache access event, so approximate the accesses with PMC2 select 26 (load instructions completed) and select 20 (store instructions completed, PMC1 or PMC2). These also count cache-inhibited accesses. PMC2 select 38 counts dcbt, dcbtst and dst line fetches that miss in the L1 data cache. On a 7448, a loop with one store in every 32 instructions counted 645840841 instructions and 19773839 L1-dcache-stores, about one store per 33 instructions. Loads and load misses are both PMC2-only events, so perf multiplexes L1-dcache-loads and L1-dcache-load-misses when both are requested, and refuses them in one group. Signed-off-by: Matt Turner --- arch/powerpc/perf/mpc7450-pmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c index 9890c87c58ef..27337a03ebde 100644 --- a/arch/powerpc/perf/mpc7450-pmu.c +++ b/arch/powerpc/perf/mpc7450-pmu.c @@ -362,9 +362,9 @@ static int mpc7450_generic_events[] = { */ static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ - [C(OP_READ)] = { 0, 0x225 }, - [C(OP_WRITE)] = { 0, 0x227 }, - [C(OP_PREFETCH)] = { 0, 0 }, + [C(OP_READ)] = { 0x21a, 0x225 }, + [C(OP_WRITE)] = { 0x014, 0x227 }, + [C(OP_PREFETCH)] = { 0, 0x226 }, }, [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ [C(OP_READ)] = { 0x129, 0x115 }, -- 2.55.0