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Mon, 09 Nov 2026 17:47:12 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:8bc4:8aec:108d:7a04]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-67c589e9b4csm693780d50.15.2026.11.09.17.47.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 17:47:12 -0800 (PST) From: Matt Turner Date: Mon, 09 Nov 2026 20:47:04 -0500 Subject: [PATCH 5/8] powerpc/perf: mpc7450: Add the PMC6 L3 events to the alternatives table X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261109-ppc32-perf-v1-5-a6e8a55b3b48@gmail.com> References: <20261109-ppc32-perf-v1-0-a6e8a55b3b48@gmail.com> In-Reply-To: <20261109-ppc32-perf-v1-0-a6e8a55b3b48@gmail.com> To: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , "Ritesh Harjani (IBM)" , Shrikanth Hegde , Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1891; i=mattst88@gmail.com; h=from:subject:message-id; bh=l5OzSa/snacUuw4Hvm7vZ0uo46L9Lthln/uI94gjUHM=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLI+lU+5+3rXyqtMKy9KT6nycVtaX2x669insDbO+w8bS nh+bn+9rOMjC4MYF8NMMUWWuPWKLLPadiz1OS39C2YOKxPIEGmRBgYgYGHgy03MKzXSMdIz1TbU MwQydIziIXJ6DBqZxcWlqUW6aQVFDnn5JYklmfl5xXr5Bal5BekFemmZaSUZGflFxalAI/TyUkt MXR3djAwNTCwdLcycLBxNTZydnQyd3BwdnV2djCzNTQycLR1NXC3NGbg4BWCuuSbD8Jt1j2r9+7 f5apctb2kVbS6YXl/9f4qJ1eP2STbP1s6OkOBjZFjR2G6rf2vdDqO3R5/OOXVZLu6VD3MDX83t3 Xcb1nhe0GYCAA== X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A PMC6 repeats five L3 events at a second select value that the alternatives table doesn't list: 0x61f L3 hits, also 0x503 and 0x603 0x620 L3 misses, also 0x514 and 0x61e 0x621 L3 instruction misses, also 0x505 and 0x605 0x622 L3 data misses, also 0x507 and 0x607 0x625 L3 touch hits, also 0x50e and 0x60e Each is the same event as the PMC5 code, so add them to its row. The scheduler can then move them to PMC5 when PMC6 is taken. Not tested on hardware with an L3; the 7448 has none. Signed-off-by: Matt Turner --- arch/powerpc/perf/mpc7450-pmu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c index 27337a03ebde..b2fe977cea16 100644 --- a/arch/powerpc/perf/mpc7450-pmu.c +++ b/arch/powerpc/perf/mpc7450-pmu.c @@ -185,18 +185,18 @@ static int mpc7450_get_constraint(u64 event, unsigned long *maskp, static const unsigned int event_alternatives[][MAX_ALT] = { { 0x217, 0x317 }, /* PM_L1_DCACHE_MISS */ { 0x502, 0x602 }, /* PM_L2_HIT */ - { 0x503, 0x603 }, /* PM_L3_HIT */ + { 0x503, 0x603, 0x61f }, /* PM_L3_HIT */ { 0x504, 0x604 }, /* PM_L2_ICACHE_MISS */ - { 0x505, 0x605 }, /* PM_L3_ICACHE_MISS */ + { 0x505, 0x605, 0x621 }, /* PM_L3_ICACHE_MISS */ { 0x506, 0x606 }, /* PM_L2_DCACHE_MISS */ - { 0x507, 0x607 }, /* PM_L3_DCACHE_MISS */ + { 0x507, 0x607, 0x622 }, /* PM_L3_DCACHE_MISS */ { 0x50a, 0x623 }, /* PM_LD_HIT_L3 */ { 0x50b, 0x624 }, /* PM_ST_HIT_L3 */ { 0x50d, 0x60d }, /* PM_L2_TOUCH_HIT */ - { 0x50e, 0x60e }, /* PM_L3_TOUCH_HIT */ + { 0x50e, 0x60e, 0x625 }, /* PM_L3_TOUCH_HIT */ { 0x512, 0x612 }, /* PM_INT_LOCAL */ { 0x513, 0x61d }, /* PM_L2_MISS */ - { 0x514, 0x61e }, /* PM_L3_MISS */ + { 0x514, 0x61e, 0x620 }, /* PM_L3_MISS */ }; /* -- 2.55.0