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Sun, 08 Nov 2026 18:14:40 -0800 (PST) Received: from mparker-home-xcrbr.sjc.aristanetworks.com ([74.123.28.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-372669d2826sm9392155eec.29.2026.11.08.18.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 18:14:40 -0800 (PST) From: Matthew Parker To: pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Matthew Parker , Adam Calabrigo Subject: [PATCH v3] mtd: spi-nor: gigadevice: Add support for GigaDevice GD25B512 Date: Mon, 9 Nov 2026 02:14:35 +0000 Message-ID: <20261109021435.904625-1-mparker@arista.com> X-Mailer: git-send-email 2.51.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for the GigaDevice GD25B512 512Mbit (64 MiB) SPI NOR flash. The chip exposes valid JESD216B SFDP tables including 4-byte address instruction tables, from which geometry and opcodes are discovered. Status register locking is enabled. Status register block protection is enabled using 4 BP bits (BP0-BP3) to cover the full 64 MiB address range. Read, write, and erase functionality across the full memory array have been tested on hardware. Cc: stable@vger.kernel.org # v6.1+ Co-developed-by: Adam Calabrigo Signed-off-by: Adam Calabrigo Signed-off-by: Matthew Parker --- v2: - Drop .fixup_flags per modern SFDP discovery conventions. v3: - Add SPI_NOR_4BIT_BP flag to .flags. drivers/mtd/spi-nor/gigadevice.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c index 6a2e6ebda148..113db85f7bd2 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -64,6 +64,9 @@ static const struct flash_info gigadevice_nor_parts[] = { .id = SNOR_ID(0xc8, 0x40, 0x19), .name = "gd25q256", .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6, + }, { + .id = SNOR_ID(0xc8, 0x47, 0x1a), + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP, }, { .id = SNOR_ID(0xc8, 0x60, 0x16), .name = "gd25lq32", -- 2.51.0