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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cdb9681385fsm1180899a12.6.2026.11.08.21.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 21:29:09 -0800 (PST) From: Shan-Chun Hung To: ychuang3@nuvoton.com, schung@nuvoton.com, vkoul@kernel.org, Frank.Li@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, kees@kernel.org, gustavoars@kernel.org, linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org Cc: Shan-Chun Hung Subject: [PATCH v2 1/2] dt-bindings: dma: nuvoton,ma35d1-pdma: Document MA35D1 PDMA controller Date: Mon, 9 Nov 2026 13:28:59 +0800 Message-Id: <20261109052900.2960473-2-shanchun1218@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261109052900.2960473-1-shanchun1218@gmail.com> References: <20261109052900.2960473-1-shanchun1218@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add binding for Nuvoton MA35D1 PDMA controller. Signed-off-by: Shan-Chun Hung --- .../bindings/dma/nuvoton,ma35d1-pdma.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml diff --git a/Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml b/Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml new file mode 100644 index 000000000000..d05971662a5d --- /dev/null +++ b/Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/nuvoton,ma35d1-pdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 PDMA controller + +description: + The MA35D1 SoC has four Peripheral DMA (PDMA) controllers. Each controller + has 10 channels and performs memory-to-memory, memory-to-peripheral and + peripheral-to-memory transfers. + +maintainers: + - Shan-Chun Hung + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + const: nuvoton,ma35d1-pdma + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + "#dma-cells": + const: 2 + description: + The first cell is the PDMA channel number. The second cell is the + peripheral request source number, as listed in the reference manual. + +required: + - compatible + - reg + - clocks + - interrupts + - "#dma-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dma-controller@40080000 { + compatible = "nuvoton,ma35d1-pdma"; + reg = <0x0 0x40080000 0x0 0x2000>; + interrupts = ; + clocks = <&clk PDMA0_GATE>; + resets = <&sys MA35D1_RESET_PDMA0>; + #dma-cells = <2>; + }; + }; + +... -- 2.25.1