From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=91.218.175.197 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794213151; b=Y0QCI+sQ3T8HRLydCYe3dcOIAdK7XzLn762TZasZ5ZRJSAi3014lbkTlKbv+YT930Ck9 TkYu4QULoboDsKFMMd0vcktZnkEGV0tsLN2WKPMSfvx+cv97xxScWZ6RudliMWpjpFFAW BiXHGVjGQVA8wfueHTMFqQZUuKKRQGEfhoTGSPnkeFi4fvnOFL8wwnsxpGk/G1mijI4Cp 1Qq8Y6jwYHlG6LQnqPcMn7wxvEHBAvhNzg104v/Mftbwy80hpJtnjMu1lPHnifNK6lZ0W algDixwjGeCx/CQ1xnntJxwXTExsgSaFGxsYcasIvFa0pBh8KR/+ItgSJUTUAAXDpeQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794213151; h=DMARC-Filter:X-Envelope-To:DKIM-Signature:X-Envelope-To:Received: X-Mizu-Trace-ID:X-Migadu-Flow:From:To:Cc:Subject:Date:Message-ID: X-Mailer:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding; bh=k8Xd/+fGnS2qXx5edt8NtESRbuDHSi6WwC92d90oCr8=; b=I3aasNssYTBH5nKNoFuVaRVacuJuN+mvkrr5LH7yRsx8L22/29F2hiODzHVvwlrbcJS/ YtdseiSbNkMlhIvMeE/ayLLqGY0TOlmQeKylIYidVH7C9Pb8ZBlTxiWuDe6d3D36DMejm KC1t5oEnwXoeW34sDmKDxME+zVKqvirZ4RoIEHJxRRVt7GtNkqNEja2aV6cSIF8yCFfiA NL4W7FhLoy+h+UQK/GCjOBTU+U1qbk0q8Klfbc1/avW3sTDs2k+07wFq1fpiSpEZuo/CK kFSiw2pJbmrjWyCkeqeHYSzAWJWk/G5VOJRN7lgS7kn9hy5oXNBvwRH1+FxfzYOyXBQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass header.d=linux.dev header.i=@linux.dev header.a=rsa-sha256 header.s=key1 header.b=o+Yri5dd; arc=none smtp.remote-ip=91.218.175.197 Received: from mta0.migadu.com (out-197.mta0.migadu.com [91.218.175.197]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34360606D839 for ; Mon, 9 Nov 2026 08:32:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 34360606D839 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=linux.dev header.i=@linux.dev header.a=rsa-sha256 header.s=key1 header.b=o+Yri5dd X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=M0DDDg353f4NM3Zyj4GK6LS1/VFcjYOv36EOnoDnTww=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1794213148; v=1; x=1794817948; b=o+Yri5ddxSBIm7E6XBkpSHRX/eVHMi9+LuDHtlCGoWFcb73adNf3aCUnUmy4V67m6pxDX5q/ Tj76zhlBKA3+hooFH6Equ8je4+HI0nj9vlItqhQqDsE0a9jbpoOgWSwpkFzdrRAiJBP3fI6kgXe QDTiPZ5jZ+kkXrpBVelRu1qY= X-Envelope-To: linux-kernel@vger.kernel.org Received: by smtp.migadu.com with ESMTPS id b501e4074c3b4662; Mon, 09 Nov 2026 08:32:27 +0000 X-Mizu-Trace-ID: b501e4074c3b4662 X-Migadu-Flow: FLOW_OUT From: Fuad Tabba To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Joey Gouly , Suzuki K Poulose , Zenghui Yu , Steffen Eiden , Catalin Marinas , Will Deacon , Mark Rutland , Vincent Donnefort , Fuad Tabba , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/16] KVM: arm64: Advertise TCR2, SCTLR2, S1PIE and S1POE to protected VMs Date: Mon, 9 Nov 2026 08:31:57 +0000 Message-ID: <20261109083205.806619-9-fuad.tabba@linux.dev> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261109083205.806619-1-fuad.tabba@linux.dev> References: <20261109083205.806619-1-fuad.tabba@linux.dev> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Advertise FEAT_TCR2, FEAT_SCTLR2, FEAT_S1PIE and FEAT_S1POE to protected VMs, with S1POE only when the kernel supports POE, as EL2 doesn't switch the POE registers otherwise. With the fields set, vcpu_set_hcrx() sets HCRX_EL2.{TCR2En,SCTLR2En} for them, and since the previous patch their PIE and POE registers don't trap. Reset the new registers as KVM does for a non-protected vCPU. Signed-off-by: Fuad Tabba --- arch/arm64/include/asm/kvm_hyp.h | 1 + arch/arm64/kvm/arm.c | 1 + arch/arm64/kvm/hyp/nvhe/sys_regs.c | 24 +++++++++++++++++++++++- 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h index 920c1d8d45b1a..ab22b395d0908 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -151,6 +151,7 @@ extern u64 kvm_nvhe_sym(id_aa64isar2_el1_sys_val); extern u64 kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val); extern u64 kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val); extern u64 kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val); +extern u64 kvm_nvhe_sym(id_aa64mmfr3_el1_sys_val); extern u64 kvm_nvhe_sym(id_aa64smfr0_el1_sys_val); extern u64 kvm_nvhe_sym(id_aa64dfr0_el1_sys_val); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 2753686982f0b..fe60535e4f358 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2834,6 +2834,7 @@ static void kvm_hyp_init_symbols(void) kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + kvm_nvhe_sym(id_aa64mmfr3_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR3_EL1); kvm_nvhe_sym(id_aa64smfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64SMFR0_EL1); kvm_nvhe_sym(id_aa64dfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); kvm_nvhe_sym(__icache_flags) = __icache_flags; diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 78c25da737591..d186aba6aa09c 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -30,6 +30,7 @@ u64 id_aa64isar2_el1_sys_val; u64 id_aa64mmfr0_el1_sys_val; u64 id_aa64mmfr1_el1_sys_val; u64 id_aa64mmfr2_el1_sys_val; +u64 id_aa64mmfr3_el1_sys_val; u64 id_aa64smfr0_el1_sys_val; u64 id_aa64dfr0_el1_sys_val; @@ -83,6 +84,11 @@ static bool vm_has_sve(const struct kvm *kvm) return system_supports_sve() && kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_SVE); } +static bool vm_has_s1poe(const struct kvm *kvm) +{ + return system_supports_poe(); +} + /* * Definitions for features to be allowed or restricted for protected guests. * @@ -177,6 +183,14 @@ static const struct pvm_ftr_bits pvmid_aa64mmfr2[] = { FEAT_END }; +static const struct pvm_ftr_bits pvmid_aa64mmfr3[] = { + MAX_FEAT(ID_AA64MMFR3_EL1, TCRX, IMP), + MAX_FEAT(ID_AA64MMFR3_EL1, SCTLRX, IMP), + MAX_FEAT(ID_AA64MMFR3_EL1, S1PIE, IMP), + MAX_FEAT_FUNC(ID_AA64MMFR3_EL1, S1POE, IMP, vm_has_s1poe), + FEAT_END +}; + static const struct pvm_ftr_bits pvmid_aa64isar1[] = { MAX_FEAT(ID_AA64ISAR1_EL1, DPB, DPB2), MAX_FEAT_FUNC(ID_AA64ISAR1_EL1, APA, PAuth, vm_has_ptrauth), @@ -274,6 +288,8 @@ static u64 pvm_calc_id_reg(const struct kvm_vcpu *vcpu, u32 id) return get_restricted_features(vcpu, id_aa64mmfr1_el1_sys_val, pvmid_aa64mmfr1); case SYS_ID_AA64MMFR2_EL1: return get_restricted_features(vcpu, id_aa64mmfr2_el1_sys_val, pvmid_aa64mmfr2); + case SYS_ID_AA64MMFR3_EL1: + return get_restricted_features(vcpu, id_aa64mmfr3_el1_sys_val, pvmid_aa64mmfr3); case SYS_ID_AA64DFR0_EL1: return get_restricted_features(vcpu, id_aa64dfr0_el1_sys_val, pvmid_aa64dfr0); case SYS_ID_AA64MMFR4_EL1: @@ -707,7 +723,7 @@ static const struct sys_reg_desc pvm_sys_reg_descs[] = { AARCH64(SYS_ID_AA64MMFR0_EL1), AARCH64(SYS_ID_AA64MMFR1_EL1), AARCH64(SYS_ID_AA64MMFR2_EL1), - ID_UNALLOCATED(7,3), + AARCH64(SYS_ID_AA64MMFR3_EL1), ID_UNALLOCATED(7,4), ID_UNALLOCATED(7,5), ID_UNALLOCATED(7,6), @@ -793,7 +809,13 @@ static const struct sys_reg_desc_reset pvm_sys_reg_reset_vals[] = { RESET_ZERO(CPACR_EL1), RESET_VAL(CONTEXTIDR_EL1, 0x00000000dbadc0deULL), RESET_VAL(SCTLR_EL1, 0x00C50078ULL), + RESET_ZERO(SCTLR2_EL1), RESET_ZERO(TCR_EL1), + RESET_ZERO(TCR2_EL1), + RESET_UNKNOWN(PIR_EL1), + RESET_UNKNOWN(PIRE0_EL1), + RESET_UNKNOWN(POR_EL1), + RESET_UNKNOWN(POR_EL0), RESET_UNKNOWN(AFSR0_EL1), RESET_UNKNOWN(AFSR1_EL1), RESET_UNKNOWN(ESR_EL1), -- 2.47.3