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Mon, 09 Nov 2026 04:08:18 -0800 (PST) Received: from localhost ([2a00:79e0:203d:7:24d0:a2cf:66c5:ef86]) by smtp.gmail.com with UTF8SMTPSA id a92af1059eb24-1b3755e936bsm16025308c88.6.2026.11.09.04.08.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Nov 2026 04:08:17 -0800 (PST) From: Chen-Yu Tsai To: Daniel Lezcano , Thomas Gleixner , Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , Luca Leonardo Scorcia , Ryan Brue , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] clocksource/drivers/timer-mediatek: Don't override the arch timer sched_clock Date: Mon, 9 Nov 2026 20:07:56 +0800 Message-ID: <20261109120757.847266-1-wenst@chromium.org> X-Mailer: git-send-email 2.56.0.455.g6c5a503b38-goog X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Since the driver was converted to a platform driver, the GPT probes late, after the architected timer has registered itself as sched_clock. sched_clock_register() only refuses counters with a lower rate, and sched_clock has no notion of priority, so the 32-bit GPT counter, which runs at the same 13 MHz as the arch timer on MT8173, replaces the 56-bit arch timer counter as sched_clock: sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns ... sched_clock: 32 bits at 13MHz, resolution 76ns, wraps every 165191050201ns Before the conversion, both drivers used TIMER_OF_DECLARE and timer-mediatek.o is linked before arm_arch_timer.o, so the arch timer registered last and won. The narrower GPT counter wraps more often and is slower to read over MMIO than the arch timer system register. Doing the switch at runtime also runs enable_sched_clock_irqtime(), which may sleep, with interrupts disabled, causing a splat. Other drivers worked around the same problem in the same way, see commit 37b8b003c483 ("clocksource/drivers/sun4i-timer: Only register a sched_clock on sun4i and sun5i") commit 10720e120e2b ("clocksource/drivers/imx-tpm: Exclude sched clock for ARM64") Only register the GPT as sched_clock if the ARM architected timer is not present. This currently includes MT6572, MT6580, MT6582, and MT6592, as seen in their respective .dtsi files. This follows the example of sun4i-timer. The analysis of the boot log and git history, and drafting of this change, were done with an AI agent. The agent originally proposed using arch_timer_get_rate(), which was replaced by the author. Manually tested on a MT8173 Hana (Telesu). Fixes: 7a097aba7255 ("clocksource/drivers/timer-mediatek: Convert to OF probing") Signed-off-by: Chen-Yu Tsai --- For the ARMv7 SoCs such as the MT2701, MT8127, and MT8135, the firmware has to correctly set the arch timer frequency, as their device trees do not have the clock-frequency property. OTOH we could let sched_clock_register() reject replacing the current counter if the new one runs at the same rate. But that would be a separate discussion: if more drivers are converted to standard platform drivers, then the probe order is no longer easily known like before by the link order. The splat is a separate issue that I already reported [1]. [1] https://lore.kernel.org/all/20261109095036.GA722431@google.com/ --- drivers/clocksource/timer-mediatek.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c index 1b2cbcc2795a..ef67cc783635 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -334,8 +335,20 @@ static int mtk_gpt_init(struct platform_device *pdev) clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC), node->name, timer_of_rate(&to), 300, 32, clocksource_mmio_readl_up); - gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC); - sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to)); + + /* + * sched_clock has no priorities; a counter with the same rate + * replaces the current one. Only these SoCs lack the ARM architected + * timer, which is otherwise the better sched_clock. + */ + if (of_machine_is_compatible("mediatek,mt6572") || + of_machine_is_compatible("mediatek,mt6580") || + of_machine_is_compatible("mediatek,mt6582") || + of_machine_is_compatible("mediatek,mt6592")) { + gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC); + sched_clock_register(mtk_gpt_read_sched_clock, 32, + timer_of_rate(&to)); + } /* Configure clock event */ mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT); -- 2.56.0.455.g6c5a503b38-goog